ADD
Add
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
04 ib | ADD AL, imm8 | I | Valid | Valid | Add imm8 to AL. |
05 iw | ADD AX, imm16 | I | Valid | Valid | Add imm16 to AX. |
05 id | ADD EAX, imm32 | I | Valid | Valid | Add imm32 to EAX. |
REX.W + 05 id | ADD RAX, imm32 | I | Valid | Not encodable | Add imm32 sign-extended to 64-bits to RAX. |
80 /0 ib | ADD r/m8, imm8 | MI | Valid | Valid | Add imm8 to r/m8. |
81 /0 iw | ADD r/m16, imm16 | MI | Valid | Valid | Add imm16 to r/m16. |
81 /0 id | ADD r/m32, imm32 | MI | Valid | Valid | Add imm32 to r/m32. |
REX.W + 81 /0 id | ADD r/m64, imm32 | MI | Valid | Not encodable | Add imm32 sign-extended to 64-bits to r/m64. |
83 /0 ib | ADD r/m16, imm8 | MI | Valid | Valid | Add sign-extended imm8 to r/m16. |
83 /0 ib | ADD r/m32, imm8 | MI | Valid | Valid | Add sign-extended imm8 to r/m32. |
REX.W + 83 /0 ib | ADD r/m64, imm8 | MI | Valid | Not encodable | Add sign-extended imm8 to r/m64. |
00 /r | ADD r/m8, r8 | MR | Valid | Valid | Add r8 to r/m8. |
01 /r | ADD r/m16, r16 | MR | Valid | Valid | Add r16 to r/m16. |
01 /r | ADD r/m32, r32 | MR | Valid | Valid | Add r32 to r/m32. |
REX.W + 01 /r | ADD r/m64, r64 | MR | Valid | Not encodable | Add r64 to r/m64. |
02 /r | ADD r8, r/m8 | RM | Valid | Valid | Add r/m8 to r8. |
03 /r | ADD r16, r/m16 | RM | Valid | Valid | Add r/m16 to r16. |
03 /r | ADD r32, r/m32 | RM | Valid | Valid | Add r/m32 to r32. |
REX.W + 03 /r | ADD r64, r/m64 | RM | Valid | Not encodable | Add r/m64 to r64. |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RM
modrm.reglectura y escrituraModRM byte, reg field (bits 5-3)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
MR
modrm.rmlectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for themmodrm.reglecturaModRM byte, reg field (bits 5-3)
MI
modrm.rmlectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for themimm8/16/32immediate after the instruction, as wide as the operand
I
AL/AX/EAX/RAXimm8/16/32immediate after the instruction, as wide as the operand
Measured cost
Loading measurements from arch-data...
Flags named
CFCarryPFParityAFAuxiliary carryZFZeroSFSignOFOverflow
Description
Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.
The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST := DEST + SRC;Flags affected
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
Exceptions
Protected mode
#GP(0) | If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Real address mode
#GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS | If a memory operand effective address is outside the SS segment limit. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Virtual-8086 mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Compatibility mode
| Same exceptions as in protected mode. |
64-bit mode
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
#GP(0) | If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |