x86 instruction reference

1134 mnemonics across 799 pages.

Alphabetical listOpcode maps

A

AAA ASCII Adjust After Addition
AAD ASCII Adjust AX Before Division
AAM ASCII Adjust AX After Multiply
AAS ASCII Adjust AL After Subtraction
ADC Add With Carry
ADCX Unsigned Integer Addition of Two Operands With Carry Flag
ADD Add
ADDPD Add Packed Double Precision Floating-Point Values
ADDPS Add Packed Single Precision Floating-Point Values
ADDSD Add Scalar Double Precision Floating-Point Values
ADDSS Add Scalar Single Precision Floating-Point Values
ADDSUBPD Packed Double Precision Floating-Point Add/Subtract
ADDSUBPS Packed Single Precision Floating-Point Add/Subtract
AESDEC Perform One Round of an AES Decryption Flow
AESDEC128KL Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-Bit
AESDEC256KL Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key
AESDECLAST Perform Last Round of an AES Decryption Flow
AESDECWIDE128KL Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks
AESDECWIDE256KL Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 Blocks
AESENC Perform One Round of an AES Encryption Flow
AESENC128KL Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key
AESENC256KL Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key
AESENCLAST Perform Last Round of an AES Encryption Flow
AESENCWIDE128KL Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 Blocks
AESENCWIDE256KL Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 Blocks
AESIMC Perform the AES InvMixColumn Transformation
AESKEYGENASSIST AES Round Key Generation Assist
AND Logical AND
ANDN Logical AND NOT
ANDNPD Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
ANDNPS Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
ANDPD Bitwise Logical AND of Packed Double Precision Floating-Point Values
ANDPS Bitwise Logical AND of Packed Single Precision Floating-Point Values
ARPL Adjust RPL Field of Segment Selector

B

BEXTR Bit Field Extract
BLENDPD Blend Packed Double Precision Floating-Point Values
BLENDPS Blend Packed Single Precision Floating-Point Values
BLENDVPD Variable Blend Packed Double Precision Floating-Point Values
BLENDVPS Variable Blend Packed Single Precision Floating-Point Values
BLSI Extract Lowest Set Isolated Bit
BLSMSK Get Mask Up to Lowest Set Bit
BLSR Reset Lowest Set Bit
BNDCL Check Lower Bound
BNDCU, BNDCN Check Upper Bound
BNDLDX Load Extended Bounds Using Address Translation
BNDMK Make Bounds
BNDMOV Move Bounds
BNDSTX Store Extended Bounds Using Address Translation
BOUND Check Array Index Against Bounds
BSF Bit Scan Forward
BSR Bit Scan Reverse
BSWAP Byte Swap
BT Bit Test
BTC Bit Test and Complement
BTR Bit Test and Reset
BTS Bit Test and Set
BZHI Zero High Bits Starting with Specified Bit Position

C

CALL Call Procedure
CBW, CWDE, CDQE Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to
CLAC Clear AC Flag in EFLAGS Register
CLC Clear Carry Flag
CLD Clear Direction Flag
CLDEMOTE Cache Line Demote
CLFLUSH Flush Cache Line
CLFLUSHOPT Flush Cache Line Optimized
CLI Clear Interrupt Flag
CLRSSBSY Clear Busy Flag in a Supervisor Shadow Stack Token
CLTS Clear Task-Switched Flag in CR0
CLUI Clear User Interrupt Flag
CLWB Cache Line Write Back
CMC Complement Carry Flag
CMOVcc Conditional Move
CMP Compare Two Operands
CMPccXADD Compare and Add if Condition is Met
CMPPD Compare Packed Double Precision Floating-Point Values
CMPPS Compare Packed Single Precision Floating-Point Values
CMPS, CMPSB, CMPSW, CMPSD, CMPSQ Compare String Operands
CMPSD Compare Scalar Double Precision Floating-Point Value
CMPSS Compare Scalar Single Precision Floating-Point Value
CMPXCHG Compare and Exchange
CMPXCHG8B, CMPXCHG16B Compare and Exchange Bytes
COMISD Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS
COMISS Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
CPUID CPU Identification
CRC32 Accumulate CRC32 Value
CVTDQ2PD Convert Packed Doubleword Integers to Packed Double Precision Floating-Point
CVTDQ2PS Convert Packed Doubleword Integers to Packed Single Precision Floating-Point
CVTPD2DQ Convert Packed Double Precision Floating-Point Values to Packed Doubleword
CVTPD2PI Convert Packed Double Precision Floating-Point Values to Packed Dword Integers
CVTPD2PS Convert Packed Double Precision Floating-Point Values to Packed Single Precision
CVTPI2PD Convert Packed Dword Integers to Packed Double Precision Floating-Point Values
CVTPI2PS Convert Packed Dword Integers to Packed Single Precision Floating-Point Values
CVTPS2DQ Convert Packed Single Precision Floating-Point Values to Packed Signed
CVTPS2PD Convert Packed Single Precision Floating-Point Values to Packed Double Precision
CVTPS2PI Convert Packed Single Precision Floating-Point Values to Packed Dword Integers
CVTSD2SI Convert Scalar Double Precision Floating-Point Value to Signed Integer
CVTSD2SS Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision
CVTSI2SD Convert Signed Integer to Scalar Double Precision Floating-Point Value
CVTSI2SS Convert Signed Integer to Scalar Single Precision Floating-Point Value
CVTSS2SD Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision
CVTSS2SI Convert Scalar Single Precision Floating-Point Value to Signed Integer
CVTTPD2DQ Convert with Truncation Packed Double Precision Floating-Point Values to
CVTTPD2PI Convert With Truncation Packed Double Precision Floating-Point Values to Packed
CVTTPS2DQ Convert With Truncation Packed Single Precision Floating-Point Values to Packed
CVTTPS2PI Convert With Truncation Packed Single Precision Floating-Point Values to Packed
CVTTSD2SI Convert With Truncation Scalar Double Precision Floating-Point Value to Signed
CVTTSS2SI Convert With Truncation Scalar Single Precision Floating-Point Value to Signed
CWD, CDQ, CQO Convert Word to Doubleword/Convert Doubleword to Quadword

D

DAA Decimal Adjust AL After Addition
DAS Decimal Adjust AL After Subtraction
DEC Decrement by 1
DIV Unsigned Divide
DIVPD Divide Packed Double Precision Floating-Point Values
DIVPS Divide Packed Single Precision Floating-Point Values
DIVSD Divide Scalar Double Precision Floating-Point Value
DIVSS Divide Scalar Single Precision Floating-Point Values
DPPD Dot Product of Packed Double Precision Floating-Point Values
DPPS Dot Product of Packed Single Precision Floating-Point Values

E

EMMS Empty MMX Technology State
ENCODEKEY128 Encode 128-Bit Key With Key Locker
ENCODEKEY256 Encode 256-Bit Key With Key Locker
ENDBR32 Terminate an Indirect Branch in 32-bit and Compatibility Mode
ENDBR64 Terminate an Indirect Branch in 64-bit Mode
ENQCMD Enqueue Command
ENQCMDS Enqueue Command Supervisor
ENTER Make Stack Frame for Procedure Parameters
ERETS Event Return to Supervisor
ERETU Event Return to User
EXTRACTPS Extract Packed Floating-Point Values

F

F2XM1 Compute 2x1
FABS Absolute Value
FADD, FADDP, FIADD Add
FBLD Load Binary Coded Decimal
FBSTP Store BCD Integer and Pop
FCHS Change Sign
FCLEX, FNCLEX Clear Exceptions
FCMOVcc Floating-Point Conditional Move
FCOM, FCOMP, FCOMPP Compare Floating-Point Values
FCOMI, FCOMIP, FUCOMI, FUCOMIP Compare Floating-Point Values and Set EFLAGS
FCOS Cosine
FDECSTP Decrement Stack-Top Pointer
FDIV, FDIVP, FIDIV Divide
FDIVR, FDIVRP, FIDIVR Reverse Divide
FFREE Free Floating-Point Register
FICOM, FICOMP Compare Integer
FILD Load Integer
FINCSTP Increment Stack-Top Pointer
FINIT, FNINIT Initialize Floating-Point Unit
FIST, FISTP Store Integer
FISTTP Store Integer With Truncation
FLD Load Floating-Point Value
FLDCW Load x87 FPU Control Word
FLDENV Load x87 FPU Environment
FMUL, FMULP, FIMUL Multiply
FNOP No Operation
FPATAN Partial Arctangent
FPREM Partial Remainder
FPREM1 Partial Remainder
FPTAN Partial Tangent
FRNDINT Round to Integer
FRSTOR Restore x87 FPU State
FSAVE, FNSAVE Store x87 FPU State
FSCALE Scale
FSIN Sine
FSINCOS Sine and Cosine
FSQRT Square Root
FST, FSTP Store Floating-Point Value
FSTCW, FNSTCW Store x87 FPU Control Word
FSTENV, FNSTENV Store x87 FPU Environment
FSTSW, FNSTSW Store x87 FPU Status Word
FSUB, FSUBP, FISUB Subtract
FSUBR, FSUBRP, FISUBR Reverse Subtract
FTST TEST
FUCOM, FUCOMP, FUCOMPP Unordered Compare Floating-Point Values
FXAM Examine Floating-Point
FXCH Exchange Register Contents
FXRSTOR Restore x87 FPU, MMX, XMM, and MXCSR State
FXSAVE Save x87 FPU, MMX Technology, and SSE State
FXTRACT Extract Exponent and Significand
FYL2X Compute y log2x
FYL2XP1 Compute y log2(x +1)

G

GETSEC[CAPABILITIES] Report the SMX Capabilities
GETSEC[ENTERACCS] Execute Authenticated Chipset Code
GETSEC[EXITAC] Exit Authenticated Code Execution Mode
GETSEC[PARAMETERS] Report the SMX Parameters
GETSEC[SENTER] Enter a Measured Environment
GETSEC[SEXIT] Exit Measured Environment
GETSEC[SMCTRL] SMX Mode Control
GETSEC[WAKEUP] Wake Up Sleeping Processors in Measured Environment
GF2P8AFFINEINVQB Galois Field Affine Transformation Inverse
GF2P8AFFINEQB Galois Field Affine Transformation
GF2P8MULB Galois Field Multiply Bytes

H

HADDPD Packed Double Precision Floating-Point Horizontal Add
HADDPS Packed Single Precision Floating-Point Horizontal Add
HLT Halt
HRESET History Reset
HSUBPD Packed Double Precision Floating-Point Horizontal Subtract
HSUBPS Packed Single Precision Floating-Point Horizontal Subtract

I

IDIV Signed Divide
IMUL Signed Multiply
IN Input From Port
INC Increment by 1
INCSSPD, INCSSPQ Increment Shadow Stack Pointer
INS, INSB, INSW, INSD Input from Port to String
INSERTPS Insert Scalar Single Precision Floating-Point Value
INT n, INTO, INT3, INT1 Call to Interrupt Procedure
INVD Invalidate Internal Caches
INVLPG Invalidate TLB Entries
INVPCID Invalidate Process-Context Identifier
IRET, IRETD, IRETQ Interrupt Return

J

Jcc Jump if Condition Is Met
JMP Jump

K

KADDW, KADDB, KADDQ, KADDD ADD Two Masks
KANDNW, KANDNB, KANDNQ, KANDND Bitwise Logical AND NOT Masks
KANDW, KANDB, KANDQ, KANDD Bitwise Logical AND Masks
KMOVW, KMOVB, KMOVQ, KMOVD Move From and to Mask Registers
KNOTW, KNOTB, KNOTQ, KNOTD NOT Mask Register
KORTESTW, KORTESTB, KORTESTQ, KORTESTD OR Masks and Set Flags
KORW, KORB, KORQ, KORD Bitwise Logical OR Masks
KSHIFTLW, KSHIFTLB, KSHIFTLQ, KSHIFTLD Shift Left Mask Registers
KSHIFTRW, KSHIFTRB, KSHIFTRQ, KSHIFTRD Shift Right Mask Registers
KTESTW, KTESTB, KTESTQ, KTESTD Packed Bit Test Masks and Set Flags
KUNPCKBW, KUNPCKWD, KUNPCKDQ Unpack for Mask Registers
KXNORW, KXNORB, KXNORQ, KXNORD Bitwise Logical XNOR Masks
KXORW, KXORB, KXORQ, KXORD Bitwise Logical XOR Masks

L

LAHF Load Status Flags Into AH Register
LAR Load Access Rights
LDDQU Load Unaligned Integer 128 Bits
LDMXCSR Load MXCSR Register
LDS, LES, LFS, LGS, LSS Load Far Pointer
LDTILECFG Load Tile Configuration
LEA Load Effective Address
LEAVE High Level Procedure Exit
LFENCE Load Fence
LGDT, LIDT Load Global/Interrupt Descriptor Table Register
LKGS Load Kernel GS Base
LLDT Load Local Descriptor Table Register
LMSW Load Machine Status Word
LOADIWKEY Load Internal Wrapping Key With Key Locker
LOCK Assert LOCK# Signal Prefix
LODS, LODSB, LODSW, LODSD, LODSQ Load String
LOOP, LOOPcc Loop According to ECX Counter
LSL Load Segment Limit
LTR Load Task Register
LZCNT Count the Number of Leading Zero Bits

M

MASKMOVDQU Store Selected Bytes of Double Quadword
MASKMOVQ Store Selected Bytes of Quadword
MAXPD Maximum of Packed Double Precision Floating-Point Values
MAXPS Maximum of Packed Single Precision Floating-Point Values
MAXSD Return Maximum Scalar Double Precision Floating-Point Value
MAXSS Return Maximum Scalar Single Precision Floating-Point Value
MFENCE Memory Fence
MINPD Minimum of Packed Double Precision Floating-Point Values
MINPS Minimum of Packed Single Precision Floating-Point Values
MINSD Return Minimum Scalar Double Precision Floating-Point Value
MINSS Return Minimum Scalar Single Precision Floating-Point Value
MONITOR Set Up Monitor Address
MOV Move
MOV Move to/from Control Registers
MOV Move to/from Debug Registers
MOVAPD Move Aligned Packed Double Precision Floating-Point Values
MOVAPS Move Aligned Packed Single Precision Floating-Point Values
MOVBE Move Data After Swapping Bytes
MOVD, MOVQ Move Doubleword/Move Quadword
MOVDDUP Replicate Double Precision Floating-Point Values
MOVDIR64B Move 64 Bytes as Direct Store
MOVDIRI Move Doubleword as Direct Store
MOVDQ2Q Move Quadword from XMM to MMX Technology Register
MOVDQA, VMOVDQA32, VMOVDQA64 Move Aligned Packed Integer Values
MOVDQU, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64 Move Unaligned Packed Integer Values
MOVHLPS Move Packed Single Precision Floating-Point Values High to Low
MOVHPD Move High Packed Double Precision Floating-Point Value
MOVHPS Move High Packed Single Precision Floating-Point Values
MOVLHPS Move Packed Single Precision Floating-Point Values Low to High
MOVLPD Move Low Packed Double Precision Floating-Point Value
MOVLPS Move Low Packed Single Precision Floating-Point Values
MOVMSKPD Extract Packed Double Precision Floating-Point Sign Mask
MOVMSKPS Extract Packed Single Precision Floating-Point Sign Mask
MOVNTDQ Store Packed Integers Using Non-Temporal Hint
MOVNTDQA Load Double Quadword Non-Temporal Aligned Hint
MOVNTI Store Doubleword Using Non-Temporal Hint
MOVNTPD Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint
MOVNTPS Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint
MOVNTQ Store of Quadword Using Non-Temporal Hint
MOVQ Move Quadword
MOVQ2DQ Move Quadword from MMX Technology to XMM Register
MOVS, MOVSB, MOVSW, MOVSD, MOVSQ Move Data From String to String
MOVSD Move or Merge Scalar Double Precision Floating-Point Value
MOVSHDUP Replicate Single Precision Floating-Point Values
MOVSLDUP Replicate Single Precision Floating-Point Values
MOVSS Move or Merge Scalar Single Precision Floating-Point Value
MOVSX, MOVSXD Move With Sign-Extension
MOVUPD Move Unaligned Packed Double Precision Floating-Point Values
MOVUPS Move Unaligned Packed Single Precision Floating-Point Values
MOVZX Move With Zero-Extend
MPSADBW Compute Multiple Packed Sums of Absolute Difference
MUL Unsigned Multiply
MULPD Multiply Packed Double Precision Floating-Point Values
MULPS Multiply Packed Single Precision Floating-Point Values
MULSD Multiply Scalar Double Precision Floating-Point Value
MULSS Multiply Scalar Single Precision Floating-Point Values
MULX Unsigned Multiply Without Affecting Flags
MWAIT Monitor Wait

N

NEG Two's Complement Negation
NOP No Operation
NOT One's Complement Negation

O

OR Logical Inclusive OR
ORPD Bitwise Logical OR of Packed Double Precision Floating-Point Values
ORPS Bitwise Logical OR of Packed Single Precision Floating-Point Values
OUT Output to Port
OUTS, OUTSB, OUTSW, OUTSD Output String to Port

P

PABSB, PABSW, PABSD, PABSQ Packed Absolute Value
PACKSSWB, PACKSSDW Pack With Signed Saturation
PACKUSDW Pack With Unsigned Saturation
PACKUSWB Pack With Unsigned Saturation
PADDB, PADDW, PADDD, PADDQ Add Packed Integers
PADDSB, PADDSW Add Packed Signed Integers with Signed Saturation
PADDUSB, PADDUSW Add Packed Unsigned Integers With Unsigned Saturation
PALIGNR Packed Align Right
PAND Logical AND
PANDN Logical AND NOT
PAUSE Spin Loop Hint
PAVGB, PAVGW Average Packed Integers
PBLENDVB Variable Blend Packed Bytes
PBLENDW Blend Packed Words
PBNDKB Platform Bind Key to Binary Large Object
PCLMULQDQ Carry-Less Multiplication Quadword
PCMPEQB, PCMPEQW, PCMPEQD Compare Packed Data for Equal
PCMPEQQ Compare Packed Qword Data for Equal
PCMPESTRI Packed Compare Explicit Length Strings, Return Index
PCMPESTRM Packed Compare Explicit Length Strings, Return Mask
PCMPGTB, PCMPGTW, PCMPGTD Compare Packed Signed Integers for Greater Than
PCMPGTQ Compare Packed Data for Greater Than
PCMPISTRI Packed Compare Implicit Length Strings, Return Index
PCMPISTRM Packed Compare Implicit Length Strings, Return Mask
PCONFIG Platform Configuration
PDEP Parallel Bits Deposit
PEXT Parallel Bits Extract
PEXTRB, PEXTRD, PEXTRQ Extract Byte/Dword/Qword
PEXTRW Extract Word
PHADDSW Packed Horizontal Add and Saturate
PHADDW, PHADDD Packed Horizontal Add
PHMINPOSUW Packed Horizontal Word Minimum
PHSUBSW Packed Horizontal Subtract and Saturate
PHSUBW, PHSUBD Packed Horizontal Subtract
PINSRB, PINSRD, PINSRQ Insert Byte/Dword/Qword
PINSRW Insert Word
PMADDUBSW Multiply and Add Packed Signed and Unsigned Bytes
PMADDWD Multiply and Add Packed Integers
PMAXSB, PMAXSW, PMAXSD, PMAXSQ Maximum of Packed Signed Integers
PMAXUB, PMAXUW Maximum of Packed Unsigned Integers
PMAXUD, PMAXUQ Maximum of Packed Unsigned Integers
PMINSB, PMINSW Minimum of Packed Signed Integers
PMINSD, PMINSQ Minimum of Packed Signed Integers
PMINUB, PMINUW Minimum of Packed Unsigned Integers
PMINUD, PMINUQ Minimum of Packed Unsigned Integers
PMOVMSKB Move Byte Mask Op/ 64/32 bit CPUID
PMOVSX Packed Move With Sign Extend
PMOVZX Packed Move With Zero Extend
PMULDQ Multiply Packed Doubleword Integers
PMULHRSW Packed Multiply High With Round and Scale
PMULHUW Multiply Packed Unsigned Integers and Store High Result
PMULHW Multiply Packed Signed Integers and Store High Result
PMULLD, PMULLQ Multiply Packed Integers and Store Low Result
PMULLW Multiply Packed Signed Integers and Store Low Result
PMULUDQ Multiply Packed Unsigned Doubleword Integers
POP Pop a Value From the Stack
POPA, POPAD Pop All General-Purpose Registers
POPCNT Return the Count of Number of Bits Set to 1
POPF, POPFD, POPFQ Pop Stack Into EFLAGS Register
POR Bitwise Logical OR
PREFETCHh Prefetch Data Into Caches
PREFETCHW Prefetch Data Into Caches in Anticipation of a Write
PREFETCHWT1 Prefetch Vector Data Into Caches With Intent to Write and T1 Hint
PSADBW Compute Sum of Absolute Differences
PSHUFB Packed Shuffle Bytes
PSHUFD Shuffle Packed Doublewords
PSHUFHW Shuffle Packed High Words
PSHUFLW Shuffle Packed Low Words
PSHUFW Shuffle Packed Words
PSIGNB, PSIGNW, PSIGND Packed SIGN
PSLLDQ Shift Double Quadword Left Logical
PSLLW, PSLLD, PSLLQ Shift Packed Data Left Logical
PSRAW, PSRAD, PSRAQ Shift Packed Data Right Arithmetic
PSRLDQ Shift Double Quadword Right Logical
PSRLW, PSRLD, PSRLQ Shift Packed Data Right Logical
PSUBB, PSUBW, PSUBD Subtract Packed Integers
PSUBQ Subtract Packed Quadword Integers
PSUBSB, PSUBSW Subtract Packed Signed Integers With Signed Saturation
PSUBUSB, PSUBUSW Subtract Packed Unsigned Integers With Unsigned Saturation
PTEST Logical Compare
PTWRITE Write Data to a Processor Trace Packet
PUNPCKHBW, PUNPCKHWD, PUNPCKHDQ, PUNPCKHQDQ Unpack High Data
PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, PUNPCKLQDQ Unpack Low Data
PUSH Push Word, Doubleword, or Quadword Onto the Stack
PUSHA, PUSHAD Push All General-Purpose Registers
PUSHF, PUSHFD, PUSHFQ Push EFLAGS Register Onto the Stack
PXOR Logical Exclusive OR

R

RCL, RCR, ROL, ROR Rotate
RCPPS Compute Reciprocals of Packed Single Precision Floating-Point Values
RCPSS Compute Reciprocal of Scalar Single Precision Floating-Point Values
RDFSBASE, RDGSBASE Read FS/GS Segment Base
RDMSR Read From Model Specific Register
RDMSRLIST Read List of Model Specific Registers
RDPID Read Processor ID
RDPKRU Read Protection Key Rights for User Pages
RDPMC Read Performance-Monitoring Counters
RDRAND Read Random Number
RDSEED Read Random SEED
RDSSPD, RDSSPQ Read Shadow Stack Pointer
RDTSC Read Time-Stamp Counter
RDTSCP Read Time-Stamp Counter and Processor ID
REP Repeat String Operation (Prefix)
REPE, REPZ Repeat String Operation While Zero (Prefix)
REPNE, REPNZ Repeat String Operation While Not Zero (Prefix)
RET Return From Procedure
ROUNDPD Round Packed Double Precision Floating-Point Values
ROUNDPS Round Packed Single Precision Floating-Point Values
ROUNDSD Round Scalar Double Precision Floating-Point Values
ROUNDSS Round Scalar Single Precision Floating-Point Values
RSM Resume From System Management Mode
RSQRTPS Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point
RSQRTSS Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point Value
RSTORSSP Restore Saved Shadow Stack Pointer

S

SAHF Store AH Into Flags
SAL, SAR, SHL, SHR Shift
SARX, SHLX, SHRX Shift Without Affecting Flags
SAVEPREVSSP Save Previous Shadow Stack Pointer
SBB Integer Subtraction With Borrow
SCAS, SCASB, SCASW, SCASD Scan String
SENDUIPI Send User Interprocessor Interrupt
SERIALIZE Serialize Instruction Execution
SETcc Set Byte on Condition
SETSSBSY Mark Shadow Stack Busy
SFENCE Store Fence
SGDT Store Global Descriptor Table Register
SHA1MSG1 Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
SHA1MSG2 Perform a Final Calculation for the Next Four SHA1 Message Dwords
SHA1NEXTE Calculate SHA1 State Variable E After Four Rounds
SHA1RNDS4 Perform Four Rounds of SHA1 Operation
SHA256MSG1 Perform an Intermediate Calculation for the Next Four SHA256 Message
SHA256MSG2 Perform a Final Calculation for the Next Four SHA256 Message Dwords
SHA256RNDS2 Perform Two Rounds of SHA256 Operation
SHLD Double Precision Shift Left
SHRD Double Precision Shift Right
SHUFPD Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values
SHUFPS Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values
SIDT Store Interrupt Descriptor Table Register
SLDT Store Local Descriptor Table Register
SMSW Store Machine Status Word
SQRTPD Square Root of Double Precision Floating-Point Values
SQRTPS Square Root of Single Precision Floating-Point Values
SQRTSD Compute Square Root of Scalar Double Precision Floating-Point Value
SQRTSS Compute Square Root of Scalar Single Precision Value
STAC Set AC Flag in EFLAGS Register
STC Set Carry Flag
STD Set Direction Flag
STI Set Interrupt Flag
STMXCSR Store MXCSR Register State
STOS, STOSB, STOSW, STOSD, STOSQ Store String
STR Store Task Register
STTILECFG Store Tile Configuration
STUI Set User Interrupt Flag
SUB Subtract
SUBPD Subtract Packed Double Precision Floating-Point Values
SUBPS Subtract Packed Single Precision Floating-Point Values
SUBSD Subtract Scalar Double Precision Floating-Point Value
SUBSS Subtract Scalar Single Precision Floating-Point Value
SWAPGS Swap GS Base Register
SYSCALL Fast System Call
SYSENTER Fast System Call
SYSEXIT Fast Return from Fast System Call
SYSRET Return From Fast System Call

T

TCMMIMFP16PS, TCMMRLFP16PS Matrix Multiplication of Complex Tiles Accumulated into
TDPBF16PS Dot Product of BF16 Tiles Accumulated into Packed Single Precision Tile
TDPBSSD, TDPBSUD, TDPBUSD, TDPBUUD Dot Product of Signed/Unsigned Bytes with Dword
TDPFP16PS Dot Product of FP16 Tiles Accumulated into Packed Single Precision Tile
TEST Logical Compare
TESTUI Determine User Interrupt Flag
TILELOADD, TILELOADDT1 Load Tile
TILERELEASE Release Tile Op/ 64/32 bit CPUID Feature
TILESTORED Store Tile
TILEZERO Zero Tile
TPAUSE Timed PAUSE
TZCNT Count the Number of Trailing Zero Bits

U

UCOMISD Unordered Compare Scalar Double Precision Floating-Point Values and Set EFLAGS
UCOMISS Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS
UD Undefined Instruction
UIRET User-Interrupt Return
UMONITOR User Level Set Up Monitor Address
UMWAIT User Level Monitor Wait
UNPCKHPD Unpack and Interleave High Packed Double Precision Floating-Point Values
UNPCKHPS Unpack and Interleave High Packed Single Precision Floating-Point Values
UNPCKLPD Unpack and Interleave Low Packed Double Precision Floating-Point Values
UNPCKLPS Unpack and Interleave Low Packed Single Precision Floating-Point Values

V

V4FMADDPS, V4FNMADDPS Packed Single Precision Floating-Point Fused Multiply-Add
V4FMADDSS, V4FNMADDSS Scalar Single Precision Floating-Point Fused Multiply-Add
VADDPH Add Packed FP16 Values
VADDSH Add Scalar FP16 Values
VALIGND, VALIGNQ Align Doubleword/Quadword Vectors
VBCSTNEBF162PS Load BF16 Element and Convert to FP32 Element With Broadcast
VBCSTNESH2PS Load FP16 Element and Convert to FP32 Element with Broadcast
VBLENDMPD, VBLENDMPS Blend Float64/Float32 Vectors Using an OpMask Control
VBROADCAST Load with Broadcast Floating-Point Data
VCMPPH Compare Packed FP16 Values
VCMPSH Compare Scalar FP16 Values
VCOMISH Compare Scalar Ordered FP16 Values and Set EFLAGS
VCOMPRESSPD Store Sparse Packed Double Precision Floating-Point Values Into Dense
VCOMPRESSPS Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
VCVTDQ2PH Convert Packed Signed Doubleword Integers to Packed FP16 Values
VCVTNE2PS2BF16 Convert Two Packed Single Data to One Packed BF16 Data
VCVTNEEBF162PS Convert Even Elements of Packed BF16 Values to FP32 Values
VCVTNEEPH2PS Convert Even Elements of Packed FP16 Values to FP32 Values
VCVTNEOBF162PS Convert Odd Elements of Packed BF16 Values to FP32 Values
VCVTNEOPH2PS Convert Odd Elements of Packed FP16 Values to FP32 Values
VCVTNEPS2BF16 Convert Packed Single Data to Packed BF16 Data
VCVTPD2PH Convert Packed Double Precision FP Values to Packed FP16 Values
VCVTPD2QQ Convert Packed Double Precision Floating-Point Values to Packed Quadword
VCVTPD2UDQ Convert Packed Double Precision Floating-Point Values to Packed Unsigned
VCVTPD2UQQ Convert Packed Double Precision Floating-Point Values to Packed Unsigned
VCVTPH2DQ Convert Packed FP16 Values to Signed Doubleword Integers
VCVTPH2PD Convert Packed FP16 Values to FP64 Values
VCVTPH2PS, VCVTPH2PSX Convert Packed FP16 Values to Single Precision Floating-Point
VCVTPH2QQ Convert Packed FP16 Values to Signed Quadword Integer Values
VCVTPH2UDQ Convert Packed FP16 Values to Unsigned Doubleword Integers
VCVTPH2UQQ Convert Packed FP16 Values to Unsigned Quadword Integers
VCVTPH2UW Convert Packed FP16 Values to Unsigned Word Integers
VCVTPH2W Convert Packed FP16 Values to Signed Word Integers
VCVTPS2PH Convert Single Precision FP Value to 16-bit FP Value
VCVTPS2PHX Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
VCVTPS2QQ Convert Packed Single Precision Floating-Point Values to Packed Signed
VCVTPS2UDQ Convert Packed Single Precision Floating-Point Values to Packed Unsigned
VCVTPS2UQQ Convert Packed Single Precision Floating-Point Values to Packed Unsigned
VCVTQQ2PD Convert Packed Quadword Integers to Packed Double Precision Floating-Point
VCVTQQ2PH Convert Packed Signed Quadword Integers to Packed FP16 Values
VCVTQQ2PS Convert Packed Quadword Integers to Packed Single Precision Floating-Point
VCVTSD2SH Convert Low FP64 Value to an FP16 Value
VCVTSD2USI Convert Scalar Double Precision Floating-Point Value to Unsigned Integer
VCVTSH2SD Convert Low FP16 Value to an FP64 Value
VCVTSH2SI Convert Low FP16 Value to Signed Integer
VCVTSH2SS Convert Low FP16 Value to FP32 Value
VCVTSH2USI Convert Low FP16 Value to Unsigned Integer
VCVTSI2SH Convert a Signed Doubleword/Quadword Integer to an FP16 Value
VCVTSS2SH Convert Low FP32 Value to an FP16 Value
VCVTSS2USI Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword
VCVTTPD2QQ Convert With Truncation Packed Double Precision Floating-Point Values to
VCVTTPD2UDQ Convert With Truncation Packed Double Precision Floating-Point Values to
VCVTTPD2UQQ Convert With Truncation Packed Double Precision Floating-Point Values to
VCVTTPH2DQ Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
VCVTTPH2QQ Convert with Truncation Packed FP16 Values to Signed Quadword Integers
VCVTTPH2UDQ Convert with Truncation Packed FP16 Values to Unsigned Doubleword
VCVTTPH2UQQ Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
VCVTTPH2UW Convert Packed FP16 Values to Unsigned Word Integers
VCVTTPH2W Convert Packed FP16 Values to Signed Word Integers
VCVTTPS2QQ Convert With Truncation Packed Single Precision Floating-Point Values to
VCVTTPS2UDQ Convert With Truncation Packed Single Precision Floating-Point Values to
VCVTTPS2UQQ Convert With Truncation Packed Single Precision Floating-Point Values to
VCVTTSD2USI Convert With Truncation Scalar Double Precision Floating-Point Value to
VCVTTSH2SI Convert with Truncation Low FP16 Value to a Signed Integer
VCVTTSH2USI Convert with Truncation Low FP16 Value to an Unsigned Integer
VCVTTSS2USI Convert With Truncation Scalar Single Precision Floating-Point Value to
VCVTUDQ2PD Convert Packed Unsigned Doubleword Integers to Packed Double Precision
VCVTUDQ2PH Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
VCVTUDQ2PS Convert Packed Unsigned Doubleword Integers to Packed Single Precision
VCVTUQQ2PD Convert Packed Unsigned Quadword Integers to Packed Double Precision
VCVTUQQ2PH Convert Packed Unsigned Quadword Integers to Packed FP16 Values
VCVTUQQ2PS Convert Packed Unsigned Quadword Integers to Packed Single Precision
VCVTUSI2SD Convert Unsigned Integer to Scalar Double Precision Floating-Point Value
VCVTUSI2SH Convert Unsigned Doubleword Integer to an FP16 Value
VCVTUSI2SS Convert Unsigned Integer to Scalar Single Precision Floating-Point Value
VCVTUW2PH Convert Packed Unsigned Word Integers to FP16 Values
VCVTW2PH Convert Packed Signed Word Integers to FP16 Values
VDBPSADBW Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
VDIVPH Divide Packed FP16 Values
VDIVSH Divide Scalar FP16 Values
VDPBF16PS Dot Product of BF16 Pairs Accumulated Into Packed Single Precision
VERR, VERW Verify a Segment for Reading or Writing
VEXP2PD Approximation to the Exponential 2^x of Packed Double Precision Floating-Point
VEXP2PS Approximation to the Exponential 2^x of Packed Single Precision Floating-Point
VEXPANDPD Load Sparse Packed Double Precision Floating-Point Values From Dense Memory
VEXPANDPS Load Sparse Packed Single Precision Floating-Point Values From Dense Memory
VFCMADDCPH, VFMADDCPH Complex Multiply and Accumulate FP16 Values
VFCMADDCSH, VFMADDCSH Complex Multiply and Accumulate Scalar FP16 Values
VFCMULCPH, VFMULCPH Complex Multiply FP16 Values
VFCMULCSH, VFMULCSH Complex Multiply Scalar FP16 Values
VFIXUPIMMPD Fix Up Special Packed Float64 Values
VFIXUPIMMPS Fix Up Special Packed Float32 Values
VFIXUPIMMSD Fix Up Special Scalar Float64 Value
VFIXUPIMMSS Fix Up Special Scalar Float32 Value
VFMADD132PD, VFMADD213PD, VFMADD231PD Fused Multiply-Add of Packed Double
VFMADD132PH, VFMADD213PH, VFMADD231PH, VFNMADD132PH, VFNMADD213PH, VFNMADD231PH Fused Multiply-Add of Packed FP16 Values
VFMADD132PS, VFMADD213PS, VFMADD231PS Fused Multiply-Add of Packed Single
VFMADD132SD, VFMADD213SD, VFMADD231SD Fused Multiply-Add of Scalar Double
VFMADD132SH, VFMADD213SH, VFMADD231SH, VFNMADD132SH, VFNMADD213SH, VFNMADD231SH Fused Multiply-Add of Scalar FP16 Values
VFMADD132SS, VFMADD213SS, VFMADD231SS Fused Multiply-Add of Scalar Single Precision
VFMSUB132PD, VFMSUB213PD, VFMSUB231PD Fused Multiply-Subtract of Packed Double
VFMSUB132PH, VFMSUB213PH, VFMSUB231PH, VFNMSUB132PH, VFNMSUB213PH, VFNMSUB231PH Fused Multiply-Subtract of Packed FP16 Values
VFMSUB132PS, VFMSUB213PS, VFMSUB231PS Fused Multiply-Subtract of Packed Single
VFMSUB132SD, VFMSUB213SD, VFMSUB231SD Fused Multiply-Subtract of Scalar Double
VFMSUB132SH, VFMSUB213SH, VFMSUB231SH, VFNMSUB132SH, VFNMSUB213SH, VFNMSUB231SH Fused Multiply-Subtract of Scalar FP16 Values
VFMSUB132SS, VFMSUB213SS, VFMSUB231SS Fused Multiply-Subtract of Scalar Single
VFNMADD132PD, VFNMADD213PD, VFNMADD231PD Fused Negative Multiply-Add of Packed
VFNMADD132PS, VFNMADD213PS, VFNMADD231PS Fused Negative Multiply-Add of Packed
VFNMADD132SD, VFNMADD213SD, VFNMADD231SD Fused Negative Multiply-Add of Scalar
VFNMADD132SS, VFNMADD213SS, VFNMADD231SS Fused Negative Multiply-Add of Scalar
VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD Fused Negative Multiply-Subtract of
VFNMSUB132PS, VFNMSUB213PS, VFNMSUB231PS Fused Negative Multiply-Subtract of
VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD Fused Negative Multiply-Subtract of
VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS Fused Negative Multiply-Subtract of
VFPCLASSPD Tests Types of Packed Float64 Values
VFPCLASSPH Test Types of Packed FP16 Values
VFPCLASSPS Tests Types of Packed Float32 Values
VFPCLASSSD Tests Type of a Scalar Float64 Value
VFPCLASSSH Test Types of Scalar FP16 Values
VFPCLASSSS Tests Type of a Scalar Float32 Value
VGATHERDPD, VGATHERQPD Gather Packed Double Precision Floating-Point Values Using
VGATHERDPS, VGATHERDPD Gather Packed Single, Packed Double with Signed Dword Indices
VGATHERDPS, VGATHERQPS Gather Packed Single Precision Floating-Point Values Using
VGATHERQPS, VGATHERQPD Gather Packed Single, Packed Double with Signed Qword Indices
VGETEXPPD Convert Exponents of Packed Double Precision Floating-Point Values to Double
VGETEXPPH Convert Exponents of Packed FP16 Values to FP16 Values
VGETEXPPS Convert Exponents of Packed Single Precision Floating-Point Values to Single
VGETEXPSD Convert Exponents of Scalar Double Precision Floating-Point Value to Double
VGETEXPSH Convert Exponents of Scalar FP16 Values to FP16 Values
VGETEXPSS Convert Exponents of Scalar Single Precision Floating-Point Value to Single
VGETMANTPD Extract Float64 Vector of Normalized Mantissas From Float64 Vector
VGETMANTPH Extract FP16 Vector of Normalized Mantissas from FP16 Vector
VGETMANTPS Extract Float32 Vector of Normalized Mantissas From Float32 Vector
VGETMANTSD Extract Float64 of Normalized Mantissa From Float64 Scalar
VGETMANTSH Extract FP16 of Normalized Mantissa from FP16 Scalar
VGETMANTSS Extract Float32 Vector of Normalized Mantissa From Float32 Scalar
VMASKMOV Conditional SIMD Packed Loads and Stores
VMAXPH Return Maximum of Packed FP16 Values
VMAXSH Return Maximum of Scalar FP16 Values
VMINPH Return Minimum of Packed FP16 Values
VMINSH Return Minimum Scalar FP16 Value
VMOVSH Move Scalar FP16 Value
VMOVW Move Word
VMULPH Multiply Packed FP16 Values
VMULSH Multiply Scalar FP16 Values
VP2INTERSECTD, VP2INTERSECTQ Compute Intersection Between DWORDS/QUADWORDS to a
VP4DPWSSD Dot Product of Signed Words With Dword Accumulation (4-Iterations)
VP4DPWSSDS Dot Product of Signed Words With Dword Accumulation and Saturation
VPBLENDD Blend Packed Dwords
VPBLENDMB, VPBLENDMW Blend Byte/Word Vectors Using an Opmask Control
VPBLENDMD, VPBLENDMQ Blend Int32/Int64 Vectors Using an OpMask Control
VPBROADCAST Load Integer and Broadcast
VPBROADCASTB, VPBROADCASTW, VPBROADCASTD, VPBROADCASTQ Load With Broadcast Integer Data From General Purpose Register
VPBROADCASTM Broadcast Mask to Vector Register
VPCMPB, VPCMPUB Compare Packed Byte Values Into Mask
VPCMPD, VPCMPUD Compare Packed Integer Values Into Mask
VPCMPQ, VPCMPUQ Compare Packed Integer Values Into Mask
VPCMPW, VPCMPUW Compare Packed Word Values Into Mask
VPCOMPRESSB, VCOMPRESSW Store Sparse Packed Byte/Word Integer Values Into Dense
VPCOMPRESSD Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register
VPCOMPRESSQ Store Sparse Packed Quadword Integer Values Into Dense Memory/Register
VPCONFLICTD, VPCONFLICTQ Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense
VPDPBSUD, VPDPBSUDS, VPDPBUUD, VPDPBUUDS, VPDPBSSD, VPDPBSSDS Multiply and Add Unsigned and Signed Bytes With and Without
VPDPBUSD Multiply and Add Unsigned and Signed Bytes
VPDPBUSDS Multiply and Add Unsigned and Signed Bytes With Saturation
VPDPWSSD Multiply and Add Signed Word Integers
VPDPWSSDS Multiply and Add Signed Word Integers With Saturation
VPDPWSUD, VPDPWSUDS, VPDPWUSD, VPDPWUSDS, VPDPWUUD, VPDPWUUDS Multiply and Add Unsigned and Signed Words With and Without
VPERM2F128 Permute Floating-Point Values
VPERM2I128 Permute Integer Values
VPERMB Permute Packed Bytes Elements
VPERMD, VPERMW Permute Packed Doubleword/Word Elements
VPERMI2B Full Permute of Bytes From Two Tables Overwriting the Index
VPERMI2W, VPERMI2D, VPERMI2Q, VPERMI2PS, VPERMI2PD Full Permute From Two Tables Overwriting the Index
VPERMILPD Permute In-Lane of Pairs of Double Precision Floating-Point Values
VPERMILPS Permute In-Lane of Quadruples of Single Precision Floating-Point Values
VPERMPD Permute Double Precision Floating-Point Elements
VPERMPS Permute Single Precision Floating-Point Elements
VPERMQ Qwords Element Permutation
VPERMT2B Full Permute of Bytes From Two Tables Overwriting a Table
VPERMT2W, VPERMT2D, VPERMT2Q, VPERMT2PS, VPERMT2PD Full Permute From Two Tables Overwriting One Table
VPEXPANDB, VPEXPANDW Expand Byte/Word Values
VPEXPANDD Load Sparse Packed Doubleword Integer Values From Dense Memory/Register
VPEXPANDQ Load Sparse Packed Quadword Integer Values From Dense Memory/Register
VPGATHERDD, VPGATHERDQ Gather Packed Dword, Packed Qword With Signed Dword Indices
VPGATHERDD, VPGATHERQD Gather Packed Dword Values Using Signed Dword/Qword Indices
VPGATHERDQ, VPGATHERQQ Gather Packed Qword Values Using Signed Dword/Qword Indices
VPGATHERQD, VPGATHERQQ Gather Packed Dword, Packed Qword with Signed Qword Indices
VPLZCNTD, VPLZCNTQ Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
VPMADD52HUQ Packed Multiply of Unsigned 52-Bit Unsigned Integers and Add High 52-Bit
VPMADD52LUQ Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Products
VPMASKMOV Conditional SIMD Integer Packed Loads and Stores
VPMOVB2M, VPMOVW2M, VPMOVD2M, VPMOVQ2M Convert a Vector Register to a Mask
VPMOVDB, VPMOVSDB, VPMOVUSDB Down Convert DWord to Byte
VPMOVDW, VPMOVSDW, VPMOVUSDW Down Convert DWord to Word
VPMOVM2B, VPMOVM2W, VPMOVM2D, VPMOVM2Q Convert a Mask Register to a Vector
VPMOVQB, VPMOVSQB, VPMOVUSQB Down Convert QWord to Byte
VPMOVQD, VPMOVSQD, VPMOVUSQD Down Convert QWord to DWord
VPMOVQW, VPMOVSQW, VPMOVUSQW Down Convert QWord to Word
VPMOVWB, VPMOVSWB, VPMOVUSWB Down Convert Word to Byte
VPMULTISHIFTQB Select Packed Unaligned Bytes From Quadword Sources
VPOPCNT Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
VPROLD, VPROLVD, VPROLQ, VPROLVQ Bit Rotate Left
VPRORD, VPRORVD, VPRORQ, VPRORVQ Bit Rotate Right
VPSHLD Concatenate and Shift Packed Data Left Logical
VPSHLDV Concatenate and Variable Shift Packed Data Left Logical
VPSHRD Concatenate and Shift Packed Data Right Logical
VPSHRDV Concatenate and Variable Shift Packed Data Right Logical
VPSHUFBITQMB Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
VPSLLVW, VPSLLVD, VPSLLVQ Variable Bit Shift Left Logical
VPSRAVW, VPSRAVD, VPSRAVQ Variable Bit Shift Right Arithmetic
VPSRLVW, VPSRLVD, VPSRLVQ Variable Bit Shift Right Logical
VPTERNLOGD, VPTERNLOGQ Bitwise Ternary Logic
VPTESTMB, VPTESTMW, VPTESTMD, VPTESTMQ Logical AND and Set Mask
VPTESTNMB, VPTESTNMW, VPTESTNMD, VPTESTNMQ Logical NAND and Set
VRANGEPD Range Restriction Calculation for Packed Pairs of Float64 Values
VRANGEPS Range Restriction Calculation for Packed Pairs of Float32 Values
VRANGESD Range Restriction Calculation From a Pair of Scalar Float64 Values
VRANGESS Range Restriction Calculation From a Pair of Scalar Float32 Values
VRCP14PD Compute Approximate Reciprocals of Packed Float64 Values
VRCP14PS Compute Approximate Reciprocals of Packed Float32 Values
VRCP14SD Compute Approximate Reciprocal of Scalar Float64 Value
VRCP14SS Compute Approximate Reciprocal of Scalar Float32 Value
VRCP28PD Approximation to the Reciprocal of Packed Double Precision Floating-Point Values
VRCP28PS Approximation to the Reciprocal of Packed Single Precision Floating-Point Values
VRCP28SD Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value
VRCP28SS Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value
VRCPPH Compute Reciprocals of Packed FP16 Values
VRCPSH Compute Reciprocal of Scalar FP16 Value
VREDUCEPD Perform Reduction Transformation on Packed Float64 Values
VREDUCEPH Perform Reduction Transformation on Packed FP16 Values
VREDUCEPS Perform Reduction Transformation on Packed Float32 Values
VREDUCESD Perform a Reduction Transformation on a Scalar Float64 Value
VREDUCESH Perform Reduction Transformation on Scalar FP16 Value
VREDUCESS Perform a Reduction Transformation on a Scalar Float32 Value
VRNDSCALEPD Round Packed Float64 Values to Include a Given Number of Fraction Bits
VRNDSCALEPH Round Packed FP16 Values to Include a Given Number of Fraction Bits
VRNDSCALEPS Round Packed Float32 Values to Include a Given Number of Fraction Bits
VRNDSCALESD Round Scalar Float64 Value to Include a Given Number of Fraction Bits
VRNDSCALESH Round Scalar FP16 Value to Include a Given Number of Fraction Bits
VRNDSCALESS Round Scalar Float32 Value to Include a Given Number of Fraction Bits
VRSQRT14PD Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
VRSQRT14PS Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
VRSQRT14SD Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
VRSQRT14SS Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
VRSQRT28PD Approximation to the Reciprocal Square Root of Packed Double Precision
VRSQRT28PS Approximation to the Reciprocal Square Root of Packed Single Precision
VRSQRT28SD Approximation to the Reciprocal Square Root of Scalar Double Precision
VRSQRT28SS Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-
VRSQRTPH Compute Reciprocals of Square Roots of Packed FP16 Values
VRSQRTSH Compute Approximate Reciprocal of Square Root of Scalar FP16 Value
VSCALEFPD Scale Packed Float64 Values With Float64 Values
VSCALEFPH Scale Packed FP16 Values with FP16 Values
VSCALEFPS Scale Packed Float32 Values With Float32 Values
VSCALEFSD Scale Scalar Float64 Values With Float64 Values
VSCALEFSH Scale Scalar FP16 Values with FP16 Values
VSCALEFSS Scale Scalar Float32 Value With Float32 Value
VSHA512MSG1 Perform an Intermediate Calculation for the Next Four SHA512 Message
VSHA512MSG2 Perform a Final Calculation for the Next Four SHA512 Message Qwords
VSHA512RNDS2 Perform Two Rounds of SHA512 Operation
VSM3MSG1 Perform Initial Calculation for the Next Four SM3 Message Words
VSM3MSG2 Perform Final Calculation for the Next Four SM3 Message Words
VSM3RNDS2 Perform Two Rounds of SM3 Operation
VSM4KEY4 Perform Four Rounds of SM4 Key Expansion
VSM4RNDS4 Performs Four Rounds of SM4 Encryption
VSQRTPH Compute Square Root of Packed FP16 Values
VSQRTSH Compute Square Root of Scalar FP16 Value
VSUBPH Subtract Packed FP16 Values
VSUBSH Subtract Scalar FP16 Value
VTESTPD, VTESTPS Packed Bit Test
VUCOMISH Unordered Compare Scalar FP16 Values and Set EFLAGS
VZEROALL Zero XMM, YMM, and ZMM Registers
VZEROUPPER Zero Upper Bits of YMM and ZMM Registers

W

WAIT, FWAIT Wait
WBINVD Write Back and Invalidate Cache
WBNOINVD Write Back and Do Not Invalidate Cache
WRFSBASE, WRGSBASE Write FS/GS Segment Base
WRMSR Write to Model Specific Register
WRMSRLIST Write List of Model Specific Registers
WRMSRNS Non-Serializing Write to Model Specific Register
WRPKRU Write Data to User Page Key Register
WRSSD, WRSSQ Write to Shadow Stack
WRUSSD, WRUSSQ Write to User Shadow Stack

X

XABORT Transactional Abort
XACQUIRE, XRELEASE Hardware Lock Elision Prefix Hints
XADD Exchange and Add
XBEGIN Transactional Begin
XCHG Exchange Register/Memory With Register
XEND Transactional End
XGETBV Get Value of Extended Control Register
XLAT, XLATB Table Look-up Translation
XOR Logical Exclusive OR
XORPD Bitwise Logical XOR of Packed Double Precision Floating-Point Values
XORPS Bitwise Logical XOR of Packed Single Precision Floating-Point Values
XRESLDTRK Resume Tracking Load Addresses
XRSTOR Restore Processor Extended States
XRSTORS Restore Processor Extended States Supervisor
XSAVE Save Processor Extended States
XSAVEC Save Processor Extended States With Compaction
XSAVEOPT Save Processor Extended States Optimized
XSAVES Save Processor Extended States Supervisor
XSETBV Set Extended Control Register
XSUSLDTRK Suspend Tracking Load Addresses
XTEST Test if in Transactional Execution

The alphabetical index answers "what does this instruction do". A map answers the opposite question, the one you have when you are reading bytes: "what is opcode 8B".

A cell can hold more than one instruction. What tells them apart is shown with it: the mandatory prefix (66, F2, F3) and the ModRM reg field when the opcode extends through it (/0 to /7). REX.W does not split the map: it changes the operand size of a form that is already in the cell.

One-byte opcodes

244 occupied cells, 539 encoding forms.

High	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	ADD	ADD	ADD	ADD	ADD	ADD	PUSH	POP	OR	OR	OR	OR	OR	OR	PUSH
1	ADC	ADC	ADC	ADC	ADC	ADC	PUSH	POP	SBB	SBB	SBB	SBB	SBB	SBB	PUSH	POP
2	AND	AND	AND	AND	AND	AND		DAA	SUB	SUB	SUB	SUB	SUB	SUB		DAS
3	XOR	XOR	XOR	XOR	XOR	XOR		AAA	CMP	CMP	CMP	CMP	CMP	CMP		AAS
4	INC	INC	INC	INC	INC	INC	INC	INC	DEC	DEC	DEC	DEC	DEC	DEC	DEC	DEC
5	PUSH	PUSH	PUSH	PUSH	PUSH	PUSH	PUSH	PUSH	POP	POP	POP	POP	POP	POP	POP	POP
6	PUSHA	POPA	BOUND	ARPLMOVSX					PUSH	IMUL	PUSH	IMUL	INSREP F3	INSREP F3	OUTSREP F3	OUTSREP F3
7	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc
8	ADC /2ADD /0AND /4CMP /7OR /1SBB /3SUB /5XOR /6	ADC /2ADD /0AND /4CMP /7OR /1SBB /3SUB /5XOR /6		ADC /2ADD /0AND /4CMP /7OR /1SBB /3SUB /5XOR /6	TEST	TEST	XCHG	XCHG	MOV	MOV	MOV	MOV	MOV	LEA	MOV	POP /0
9	NOPPAUSE F3XCHG	XCHG	XCHG	XCHG	XCHG	XCHG	XCHG	XCHG	CBW	CWD	CALL	FCLEXFINITFSAVE /6FSTCW /7FSTENV /6FSTSW /7FSTSWWAIT	PUSHF	POPF	SAHF	LAHF
A	MOV	MOV	MOV	MOV	MOVSREP F3	MOVSREP F3	CMPSREPE F3REPNE F2	CMPSREPE F3REPNE F2	TEST	TEST	REP F3STOS	REP F3STOS	LODSREP F3	LODSREP F3	REPE F3REPNE F2SCAS	REPE F3REPNE F2SCAS
B	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV	MOV
C	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	RET	RET	LDS	LDS	MOV /0XABORT	MOV /0XBEGIN	ENTER	LEAVE	RET	RET	INT n	INT n	INT n	IRET
D	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	RCL /2RCL /3RCL /0RCL /1SAL /4SAL /7SAL /5	AAM	AAD	UD	XLAT	FADD /0FADDFCMOVccFCOM /2FCOMFCOM /3FCOMIFDIV /6FDIVFDIVR /7FDIVRFFREEFLDFMUL /1FMULFSTFSUB /4FSUBFSUBR /5FSUBRFUCOMFXCH	F2XM1FABSFADDFCHSFCMOVccFCOMFCOMIFCOSFDECSTPFDIVFDIVRFFREEFINCSTPFLD /0FLDFLDCW /5FLDENV /4FMULFNOPFPATANFPREMFPREM1FPTANFRNDINTFSCALEFSINFSINCOSFSQRTFST /2FSTFST /3FSTCW /7FSTENV /6FSUBFSUBRFTSTFUCOMFXAMFXCHFXTRACTFYL2XFYL2XP1	FADDFADD /0FCMOVccFCOMFCOMIFDIVFDIV /6FDIVRFDIVR /7FFREEFICOM /2FICOM /3FLDFMULFMUL /1FSTFSUBFSUB /4FSUBRFSUBR /5FUCOMFXCH	FADDFCLEXFCMOVccFCOMFCOMIFDIVFDIVRFFREEFILD /0FINITFIST /2FIST /3FISTTP /1FLD /5FLDFMULFSTFST /7FSUBFSUBRFUCOMFXCH	FADD /0FADDFCMOVccFCOM /2FCOMFCOM /3FCOMIFDIV /6FDIVFDIVR /7FDIVRFFREEFLDFMUL /1FMULFSTFSUB /4FSUBFSUBR /5FSUBRFUCOMFXCHPADDUSB VEX	FADDFCMOVccFCOMFCOMIFDIVFDIVRFFREEFISTTP /1FLD /0FLDFMULFRSTOR /4FSAVE /6FST /2FSTFST /3FSTSW /7FSUBFSUBRFUCOMFXCH	FADDFADD /0FCMOVccFCOMFCOMIFDIVFDIV /6FDIVRFDIVR /7FFREEFICOM /2FICOM /3FLDFMULFMUL /1FSTFSUBFSUB /4FSUBRFSUBR /5FUCOMFXCH	FADDFBLD /4FBSTP /6FCMOVccFCOMFCOMIFDIVFDIVRFFREEFILD /0FILD /5FIST /2FIST /3FIST /7FISTTP /1FLDFMULFSTFSTSWFSUBFSUBRFUCOMFXCH
E	LOOP	LOOP	LOOP	Jcc	IN	IN	OUT	OUT	CALL	JMP	JMP	JMP	IN	IN	OUT	OUT
F	LOCK	INT n			HLT	CMC	DIV /6IDIV /7IMUL /5MUL /4NEG /3NOT /2TEST /0	DIV /6IDIV /7IMUL /5MUL /4NEG /3NOT /2TEST /0	CLC	STC	CLI	STI	CLD	STD	DEC /1INC /0	CALL /2CALL /3DEC /1INC /0JMP /4JMP /5PUSH /6

Opcodes after 0F

234 occupied cells, 892 encoding forms.

High	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	LKGS F2 /6LLDT /2LTR /3SLDT /0STR /1VERR /4VERR /5	CLACCLUI F3ERETS F2ERETU F3INVLPG /7LGDT /2LGDT /3LMSW /6MONITORMWAITPBNDKBPCONFIGRDMSRLIST F2RDPKRURDTSCPRSTORSSP F3 /5SAVEPREVSSP F3SERIALIZESETSSBSY F3SGDT /0SIDT /1SMSW /4STACSTUI F3SWAPGSTESTUI F3UIRET F3WRMSRLIST F3WRMSRNSWRPKRUXENDXGETBVXRESLDTRK F2XSETBVXSUSLDTRK F2XTEST	LARVCVTTPD2UDQ EVEX	LSL		SYSCALL	CLTS	SYSRET	INVD	WBINVDWBNOINVD F3		UD		PREFETCHW /1PREFETCHWT1 /2
1	MOVSD F2MOVSD VEXMOVSD EVEXMOVSS F3MOVSS VEXMOVSS EVEXMOVUPD 66MOVUPD VEXMOVUPD EVEXMOVUPSMOVUPS VEXMOVUPS EVEX	MOVSD F2MOVSD VEXMOVSD EVEXMOVSS F3MOVSS VEXMOVSS EVEXMOVUPD 66MOVUPD VEXMOVUPD EVEXMOVUPSMOVUPS VEXMOVUPS EVEX	MOVDDUP F2MOVDDUP VEXMOVDDUP EVEXMOVHLPSMOVHLPS VEXMOVHLPS EVEXMOVLPD 66MOVLPD VEXMOVLPD EVEXMOVLPSMOVLPS VEXMOVLPS EVEXMOVSLDUP F3MOVSLDUP VEXMOVSLDUP EVEX	MOVLPD 66MOVLPD VEXMOVLPD EVEXMOVLPSMOVLPS VEXMOVLPS EVEX	UNPCKLPD 66UNPCKLPD VEXUNPCKLPD EVEXUNPCKLPSUNPCKLPS VEXUNPCKLPS EVEX	UNPCKHPD 66UNPCKHPD VEXUNPCKHPD EVEXUNPCKHPSUNPCKHPS VEXUNPCKHPS EVEX	MOVHPD 66MOVHPD VEXMOVHPD EVEXMOVHPSMOVHPS VEXMOVHPS EVEXMOVLHPSMOVLHPS VEXMOVLHPS EVEXMOVSHDUP F3MOVSHDUP VEXMOVSHDUP EVEX	MOVHPD 66MOVHPD VEXMOVHPD EVEXMOVHPSMOVHPS VEXMOVHPS EVEX	PREFETCHh /1PREFETCHh /2PREFETCHh /3PREFETCHh /0PREFETCHh /7PREFETCHh /6		BNDCL F3BNDCU F2BNDLDXBNDMOV 66	BNDCU F2BNDMK F3BNDMOV 66BNDSTX	CLDEMOTE /0		ENDBR32 F3ENDBR64 F3RDSSPD F3	NOP /0
2	MOVMOV /0	MOV	MOVMOV /0	MOV					MOVAPD 66MOVAPD VEXMOVAPD EVEXMOVAPSMOVAPS VEXMOVAPS EVEX	MOVAPD 66MOVAPD VEXMOVAPD EVEXMOVAPSMOVAPS VEXMOVAPS EVEX	CVTPI2PD 66CVTPI2PSCVTSI2SD F2CVTSI2SD VEXCVTSI2SD EVEXCVTSI2SS F3CVTSI2SS VEXCVTSI2SS EVEX	MOVNTPD 66MOVNTPD VEXMOVNTPD EVEXMOVNTPSMOVNTPS VEXMOVNTPS EVEX	CVTTPD2PI 66CVTTPS2PICVTTSD2SI F2CVTTSD2SI VEXCVTTSD2SI EVEXCVTTSS2SI F3CVTTSS2SI VEXCVTTSS2SI EVEX	CVTPD2PI 66CVTPS2PICVTSD2SI F2CVTSD2SI VEXCVTSD2SI EVEXCVTSS2SI F3CVTSS2SI VEXCVTSS2SI EVEX	UCOMISD 66UCOMISD VEXUCOMISD EVEXUCOMISSUCOMISS VEXUCOMISS EVEX	COMISD 66COMISD VEXCOMISD EVEXCOMISSCOMISS VEXCOMISS EVEX
3	WRMSR	RDTSC	RDMSR	RDPMC	SYSENTER	PMOVZX VEXSYSEXIT		GETSEC[CAPABILITIES]GETSEC[ENTERACCS]GETSEC[EXITAC]GETSEC[PARAMETERS]GETSEC[SENTER]GETSEC[SEXIT]GETSEC[SMCTRL]GETSEC[WAKEUP]
4	CMOVcc	CMOVccKANDW VEX	CMOVccKANDNW VEX	CMOVcc	CMOVccKNOTW VEX	CMOVccKORW VEX	CMOVccKXNORW VEX	CMOVccKXORW VEX	CMOVcc	CMOVcc	CMOVccKADDW VEX	CMOVccKUNPCKBW VEX	CMOVcc	CMOVcc	CMOVcc	CMOVcc
5	MOVMSKPD 66MOVMSKPD VEXMOVMSKPSMOVMSKPS VEX	SQRTPD 66SQRTPD VEXSQRTPD EVEXSQRTPSSQRTPS VEXSQRTPS EVEXSQRTSD F2SQRTSD VEXSQRTSD EVEXSQRTSS F3SQRTSS VEXSQRTSS EVEX	RSQRTPSRSQRTPS VEXRSQRTSS F3RSQRTSS VEX	RCPPSRCPPS VEXRCPSS F3RCPSS VEX	ANDPD 66ANDPD VEXANDPD EVEXANDPSANDPS VEXANDPS EVEX	ANDNPD 66ANDNPD VEXANDNPD EVEXANDNPSANDNPS VEXANDNPS EVEX	ORPD 66ORPD VEXORPD EVEXORPSORPS VEXORPS EVEX	XORPD 66XORPD VEXXORPD EVEXXORPSXORPS VEXXORPS EVEX	ADDPD 66ADDPD VEXADDPD EVEXADDPSADDPS VEXADDPS EVEXADDSD F2ADDSD VEXADDSD EVEXADDSS F3ADDSS VEXADDSS EVEX	MULPD 66MULPD VEXMULPD EVEXMULPSMULPS VEXMULPS EVEXMULSD F2MULSD VEXMULSD EVEXMULSS F3MULSS VEXMULSS EVEX	CVTPD2PS 66CVTPD2PS VEXCVTPD2PS EVEXCVTPS2PDCVTPS2PD VEXCVTPS2PD EVEXCVTSD2SS F2CVTSD2SS VEXCVTSD2SS EVEXCVTSS2SD F3CVTSS2SD VEXCVTSS2SD EVEX	CVTDQ2PSCVTDQ2PS VEXCVTDQ2PS EVEXCVTPS2DQ 66CVTPS2DQ VEXCVTPS2DQ EVEXCVTTPS2DQ F3CVTTPS2DQ VEXCVTTPS2DQ EVEXVCVTQQ2PS EVEX	SUBPD 66SUBPD VEXSUBPD EVEXSUBPSSUBPS VEXSUBPS EVEXSUBSD F2SUBSD VEXSUBSD EVEXSUBSS F3SUBSS VEXSUBSS EVEX	MINPD 66MINPD VEXMINPD EVEXMINPSMINPS VEXMINPS EVEXMINSD F2MINSD VEXMINSD EVEXMINSS F3MINSS VEXMINSS EVEX	DIVPD 66DIVPD VEXDIVPD EVEXDIVPSDIVPS VEXDIVPS EVEXDIVSD F2DIVSD VEXDIVSD EVEXDIVSS F3DIVSS VEXDIVSS EVEX	MAXPD 66MAXPD VEXMAXPD EVEXMAXPSMAXPS VEXMAXPS EVEXMAXSD F2MAXSD VEXMAXSD EVEXMAXSS F3MAXSS VEXMAXSS EVEX
6	PUNPCKLBWPUNPCKLBW 66PUNPCKLBW VEXPUNPCKLBW EVEX	PUNPCKLBWPUNPCKLBW 66PUNPCKLBW VEXPUNPCKLBW EVEX	PUNPCKLBWPUNPCKLBW 66PUNPCKLBW VEXPUNPCKLBW EVEX	PACKSSWBPACKSSWB 66PACKSSWB VEXPACKSSWB EVEX	PCMPGTBPCMPGTB 66PCMPGTB VEXPCMPGTB EVEX	PCMPGTBPCMPGTB 66PCMPGTB VEXPCMPGTB EVEX	PCMPGTBPCMPGTB 66	PACKUSWBPACKUSWB 66PACKUSWB VEXPACKUSWB EVEX	PUNPCKHBWPUNPCKHBW 66PUNPCKHBW VEXPUNPCKHBW EVEX	PUNPCKHBWPUNPCKHBW 66PUNPCKHBW VEXPUNPCKHBW EVEX	PUNPCKHBWPUNPCKHBW 66PUNPCKHBW VEXPUNPCKHBW EVEX	PACKSSWBPACKSSWB 66PACKSSWB VEXPACKSSWB EVEX	PUNPCKLBW 66PUNPCKLBW VEXPUNPCKLBW EVEX	PUNPCKHBW 66PUNPCKHBW VEXPUNPCKHBW EVEX	MOVDMOVD 66MOVD VEXMOVD EVEX	MOVDQA 66MOVDQA VEXMOVDQA EVEXMOVDQU F3MOVDQU VEXMOVDQU EVEXMOVQ
7	PSHUFD 66PSHUFD VEXPSHUFD EVEXPSHUFHW F3PSHUFHW VEXPSHUFHW EVEXPSHUFLW F2PSHUFLW VEXPSHUFLW EVEXPSHUFW	PSLLW /6PSLLW 66 /6PSLLW VEX /6PSLLW EVEX /6PSRAW /4PSRAW 66 /4PSRAW VEX /4PSRAW EVEX /4PSRLW /2PSRLW 66 /2PSRLW VEX /2PSRLW EVEX /2	PSLLW /6PSLLW 66 /6PSLLW VEX /6PSLLW EVEX /6PSRAW /4PSRAW 66 /4PSRAW VEX /4PSRAW EVEX /4PSRLW /2PSRLW 66 /2PSRLW VEX /2PSRLW EVEX /2VPROLD EVEX /1VPRORD EVEX /0	PSLLDQ 66 /7PSLLDQ VEX /7PSLLDQ EVEX /7PSLLW /6PSLLW 66 /6PSLLW VEX /6PSLLW EVEX /6PSRLDQ 66 /3PSRLDQ VEX /3PSRLDQ EVEX /3PSRLW /2PSRLW 66 /2PSRLW VEX /2PSRLW EVEX /2	PCMPEQBPCMPEQB 66PCMPEQB VEXPCMPEQB EVEX	PCMPEQBPCMPEQB 66PCMPEQB VEXPCMPEQB EVEX	PCMPEQBPCMPEQB 66PCMPEQB VEXPCMPEQB EVEX	EMMSVZEROALL VEXVZEROUPPER VEX	VCVTTPD2UDQ EVEXVCVTTPD2UQQ EVEXVCVTTPS2UDQ EVEXVCVTTPS2UQQ EVEXVCVTTSD2USI EVEXVCVTTSS2USI EVEX	VCVTPD2UDQ EVEXVCVTPD2UQQ EVEXVCVTPS2UDQ EVEXVCVTPS2UQQ EVEXVCVTSD2USI EVEXVCVTSS2USI EVEX	VCVTTPD2QQ EVEXVCVTTPS2QQ EVEXVCVTUDQ2PD EVEXVCVTUDQ2PS EVEXVCVTUQQ2PD EVEXVCVTUQQ2PS EVEX	VCVTPD2QQ EVEXVCVTPS2QQ EVEXVCVTUSI2SD EVEXVCVTUSI2SS EVEX	HADDPD 66HADDPD VEXHADDPS F2HADDPS VEX	HSUBPD 66HSUBPD VEXHSUBPS F2HSUBPS VEX	MOVDMOVD 66MOVD VEXMOVD EVEXMOVQ F3MOVQ VEXMOVQ EVEX	MOVDQA 66MOVDQA VEXMOVDQA EVEXMOVDQU F3MOVDQU VEXMOVDQU EVEXMOVQ
8	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc	Jcc
9	KMOVW VEXSETcc	KMOVW VEXSETcc	KMOVW VEXSETcc	KMOVW VEXSETcc	SETcc	SETcc	SETcc	SETcc	KORTESTW VEXSETcc	KTESTW VEXSETcc	SETcc	SETcc	SETcc	SETcc	SETcc	SETcc
A	PUSH	POP	CPUID	BT	SHLD	SHLD			PUSH	POP	RSM	BTS	SHRD	SHRD	CLFLUSH /7CLFLUSHOPT NFX 66 /7CLRSSBSY F3 /6CLWB 66 /6FXRSTOR /1FXSAVE /0INCSSPD F3 /5LDMXCSR /2LDMXCSR VEX /2LFENCEMFENCEPTWRITE F3 /4RDFSBASE F3 /0RDFSBASE F3 /1SFENCESTMXCSR /3STMXCSR VEX /3TPAUSE 66 /6UMONITOR F3 /6UMWAIT F2 /6WRFSBASE F3 /2WRFSBASE F3 /3XRSTOR /5XSAVE /4XSAVEOPT /6	IMUL
B	CMPXCHG	CMPXCHG	LDS	BTR	LDS	LDS	MOVZX	MOVZX	POPCNT F3	UD	BT /4BTC /7BTR /6BTS /5	BTC	BSFTZCNT F3	BSRLZCNT F3	MOVSX	MOVSX
C	XADD	XADD	CMPPD 66CMPPD VEXCMPPD EVEXCMPPSCMPPS VEXCMPPS EVEXCMPSD F2CMPSD VEXCMPSD EVEXCMPSS F3CMPSS VEXCMPSS EVEX	MOVNTI	PINSRWPINSRW 66PINSRW VEXPINSRW EVEX	PEXTRWPEXTRW 66PEXTRW VEXPEXTRW EVEX	SHUFPD 66SHUFPD VEXSHUFPD EVEXSHUFPSSHUFPS VEXSHUFPS EVEX	CMPXCHG8B /1RDPID F3 /7RDRAND NFX /6RDSEED NFX /7SENDUIPI F3 /6XRSTORS /3XSAVEC /4XSAVES /5	BSWAP	BSWAP	BSWAP	BSWAP	BSWAP	BSWAP	BSWAP	BSWAP
D	ADDSUBPD 66ADDSUBPD VEXADDSUBPS F2ADDSUBPS VEX	PSRLWPSRLW 66PSRLW VEXPSRLW EVEX	PSRLWPSRLW 66PSRLW VEXPSRLW EVEX	PSRLWPSRLW 66PSRLW VEXPSRLW EVEX	PADDBPADDB 66PADDB VEXPADDB EVEX	PMULLWPMULLW 66PMULLW VEXPMULLW EVEX	MOVDQ2Q F2MOVQ 66MOVQ VEXMOVQ EVEXMOVQ2DQ F3	PMOVMSKBPMOVMSKB 66PMOVMSKB VEX	PSUBUSBPSUBUSB 66PSUBUSB VEXPSUBUSB EVEX	PSUBUSBPSUBUSB 66PSUBUSB VEXPSUBUSB EVEX	PMINUBPMINUB 66PMINUB VEXPMINUB EVEX	PANDPAND 66PAND VEXPAND EVEX	PADDUSBPADDUSB 66PADDUSB VEXPADDUSB EVEX	PADDUSBPADDUSB 66PADDUSB VEXPADDUSB EVEX	PMAXUBPMAXUB 66PMAXUB VEXPMAXUB EVEX	PANDNPANDN 66PANDN VEXPANDN EVEX
E	PAVGBPAVGB 66PAVGB VEXPAVGB EVEX	PSRAWPSRAW 66PSRAW VEXPSRAW EVEX	PSRAWPSRAW 66PSRAW VEXPSRAW EVEX	PAVGBPAVGB 66PAVGB VEXPAVGB EVEX	PMULHUWPMULHUW 66PMULHUW VEXPMULHUW EVEX	PMULHWPMULHW 66PMULHW VEXPMULHW EVEX	CVTDQ2PD F3CVTDQ2PD VEXCVTDQ2PD EVEXCVTPD2DQ F2CVTPD2DQ VEXCVTPD2DQ EVEXCVTTPD2DQ 66CVTTPD2DQ VEXCVTTPD2DQ EVEXVCVTQQ2PD EVEX	MOVNTDQ 66MOVNTDQ VEXMOVNTDQ EVEXMOVNTQ	PSUBSBPSUBSB 66PSUBSB VEXPSUBSB EVEX	PSUBSBPSUBSB 66PSUBSB VEXPSUBSB EVEX	PMINSBPMINSB 66PMINSB VEXPMINSB EVEX	PORPOR 66POR VEXPOR EVEX	PADDSBPADDSB 66PADDSB VEXPADDSB EVEX	PADDSBPADDSB 66PADDSB VEXPADDSB EVEX	PMAXSBPMAXSB 66PMAXSB VEXPMAXSB EVEX	PXORPXOR 66PXOR VEXPXOR EVEX
F	LDDQU F2LDDQU VEX	PSLLWPSLLW 66PSLLW VEXPSLLW EVEX	PSLLWPSLLW 66	PSLLWPSLLW 66	PMULUDQPMULUDQ 66PMULUDQ VEXPMULUDQ EVEX	PMADDWDPMADDWD 66PMADDWD VEXPMADDWD EVEX	PSADBWPSADBW 66PSADBW VEXPSADBW EVEX	MASKMOVDQU 66MASKMOVDQU VEXMASKMOVQ	PSUBBPSUBB 66PSUBB VEXPSUBB EVEX	PSUBBPSUBB 66PSUBB VEXPSUBB EVEX	PSUBBPSUBB 66PSUBB VEXPSUBB EVEX	PSUBQPSUBQ 66PSUBQ VEXPSUBQ EVEX	PADDBPADDB 66PADDB VEXPADDB EVEX	PADDBPADDB 66PADDB VEXPADDB EVEX	PADDBPADDB 66PADDB VEXPADDB EVEX	UD

Opcodes after 0F 38

196 occupied cells, 501 encoding forms.

High	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	PSHUFBPSHUFB 66PSHUFB VEXPSHUFB EVEX	PHADDWPHADDW 66PHADDW VEX	PHADDWPHADDW 66PHADDW VEX	PHADDSWPHADDSW 66PHADDSW VEX	PMADDUBSWPMADDUBSW 66PMADDUBSW VEXPMADDUBSW EVEX	PHSUBWPHSUBW 66PHSUBW VEX	PHSUBWPHSUBW 66PHSUBW VEX	PHSUBSWPHSUBSW 66PHSUBSW VEX	PSIGNBPSIGNB 66PSIGNB VEX	PSIGNBPSIGNB 66PSIGNB VEX	PSIGNBPSIGNB 66PSIGNB VEX	PMULHRSWPMULHRSW 66PMULHRSW VEXPMULHRSW EVEX	VPERMILPS VEXVPERMILPS EVEX	VPERMILPD VEXVPERMILPD EVEX	VTESTPD VEX	VTESTPD VEX
1	PBLENDVB 66VPMOVWB EVEXVPSRLVW EVEX	VPMOVDB EVEXVPSRAVW EVEX	VPMOVQB EVEXVPSLLVW EVEX	VCVTPH2PS VEXVCVTPH2PS EVEXVPMOVDW EVEX	BLENDVPS 66VPMOVQW EVEXVPRORD EVEX	BLENDVPD 66VPMOVQD EVEXVPROLD EVEX	VPERMPD EVEXVPERMPS VEXVPERMPS EVEX	PTEST 66PTEST VEX	VBROADCAST VEXVBROADCAST EVEX	VBROADCAST VEXVBROADCAST EVEX	VBROADCAST VEXVBROADCAST EVEX	VBROADCAST EVEX	PABSBPABSB 66PABSB VEXPABSB EVEX	PABSBPABSB 66PABSB VEXPABSB EVEX	PABSBPABSB 66PABSB VEXPABSB EVEX	PABSB EVEX
2	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVWB EVEX	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVDB EVEX	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVQB EVEX	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVDW EVEX	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVQW EVEX	PMOVSX 66PMOVSX VEXPMOVSX EVEXVPMOVQD EVEX	VPTESTMB EVEXVPTESTNMB EVEX	VPTESTMB EVEXVPTESTNMB EVEX	PMULDQ 66PMULDQ VEXPMULDQ EVEXVPMOVM2B EVEX	PCMPEQQ 66PCMPEQQ VEXPCMPEQQ EVEXVPMOVB2M EVEX	MOVNTDQA 66MOVNTDQA VEXMOVNTDQA EVEXVPBROADCASTM EVEX	PACKUSDW 66PACKUSDW VEXPACKUSDW EVEX	VMASKMOV VEXVSCALEFPD EVEXVSCALEFPS EVEX	VMASKMOV VEXVSCALEFSD EVEXVSCALEFSS EVEX	VMASKMOV VEX	VMASKMOV VEX
3	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVWB EVEX	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVDB EVEX	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVQB EVEX	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVDW EVEX	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVQW EVEX	PMOVZX 66PMOVZX VEXPMOVZX EVEXVPMOVQD EVEX	VPERMD VEXVPERMD EVEXVPERMQ EVEX	PCMPGTQ 66PCMPGTQ VEXPCMPGTQ EVEX	PMINSB 66PMINSB VEXPMINSB EVEXVPMOVM2B EVEX	PMINSD 66PMINSD VEXPMINSD EVEXVPMOVB2M EVEX	PMINUB 66PMINUB VEXPMINUB EVEXVPBROADCASTM EVEX	PMINUD 66PMINUD VEXPMINUD EVEX	PMAXSB 66PMAXSB VEXPMAXSB EVEX	PMAXSB 66PMAXSB VEXPMAXSB EVEX	PMAXUB 66PMAXUB VEXPMAXUB EVEX	PMAXUD 66PMAXUD VEXPMAXUD EVEX
4	PMULLD 66PMULLD VEXPMULLD EVEX	PHMINPOSUW 66PHMINPOSUW VEX	VGETEXPPD EVEXVGETEXPPS EVEX	VGETEXPSD EVEXVGETEXPSS EVEX	VPLZCNTD EVEX	VPSRLVW VEXVPSRLVW EVEX	VPSRAVW VEXVPSRAVW EVEX	VPSLLVW VEXVPSLLVW EVEX		LDTILECFG VEXSTTILECFG VEXTILEZERO VEX		TILELOADD VEXTILESTORED VEX	VRCP14PD EVEXVRCP14PS EVEX	VRCP14SD EVEXVRCP14SS EVEX	VRSQRT14PD EVEXVRSQRT14PS EVEX	VRSQRT14SD EVEXVRSQRT14SS EVEX
5	VPDPBSUD VEXVPDPBUSD VEXVPDPBUSD EVEX	VPDPBSUD VEXVPDPBUSDS VEXVPDPBUSDS EVEX	VDPBF16PS EVEXVP4DPWSSD EVEXVPDPWSSD VEXVPDPWSSD EVEX	VP4DPWSSDS EVEXVPDPWSSDS VEXVPDPWSSDS EVEX	VPOPCNT EVEX	VPOPCNT EVEX			VPBROADCAST VEXVPBROADCAST EVEX	VPBROADCAST VEXVPBROADCAST EVEX	VPBROADCAST VEXVPBROADCAST EVEX	VPBROADCAST EVEX	TDPBF16PS VEXTDPFP16PS VEX		TDPBSSD VEX
6			VPEXPANDB EVEX	VPCOMPRESSB EVEX	VPBLENDMD EVEX	VBLENDMPD EVEX			VP2INTERSECTD EVEX				TCMMIMFP16PS VEX
7	VPSHLDV EVEX	VPSHLDV EVEX	VCVTNE2PS2BF16 EVEXVCVTNEPS2BF16 VEXVCVTNEPS2BF16 EVEXVPSHRDV EVEX	VPSHRDV EVEX		VPERMI2B EVEXVPERMI2W EVEX	VPERMI2W EVEX	VPERMI2W EVEX	VPBROADCAST VEXVPBROADCAST EVEX	VPBROADCAST VEXVPBROADCAST EVEX	VPBROADCASTB EVEX	VPBROADCASTB EVEX	VPBROADCASTB EVEX	VPERMT2B EVEXVPERMT2W EVEX	VPERMT2W EVEX	VPERMT2W EVEX
8			INVPCID 66	VPMULTISHIFTQB EVEX					VEXPANDPD EVEXVEXPANDPS EVEX	VPEXPANDD EVEXVPEXPANDQ EVEX	VCOMPRESSPD EVEXVCOMPRESSPS EVEX	VPCOMPRESSD EVEXVPCOMPRESSQ EVEX	VPMASKMOV VEX	VPERMB EVEXVPERMD EVEX	VPMASKMOV VEX	VPSHUFBITQMB EVEX
9	VPGATHERDD EVEXVPGATHERDD VEXVPGATHERDQ VEX	VPGATHERDD VEXVPGATHERDQ VEXVPGATHERQD EVEX	VGATHERDPD VEXVGATHERDPS EVEXVGATHERDPS VEX	VGATHERDPD VEXVGATHERDPS VEXVGATHERQPS EVEX					VFMADD132PD VEXVFMADD132PD EVEXVFMADD132PS VEXVFMADD132PS EVEX	VFMADD132SD VEXVFMADD132SD EVEXVFMADD132SS VEXVFMADD132SS EVEX	V4FMADDPS EVEXVFMSUB132PD VEXVFMSUB132PD EVEXVFMSUB132PS VEXVFMSUB132PS EVEX	V4FMADDSS EVEXVFMSUB132SD VEXVFMSUB132SD EVEXVFMSUB132SS VEXVFMSUB132SS EVEX	VFNMADD132PD VEXVFNMADD132PD EVEXVFNMADD132PS VEXVFNMADD132PS EVEX	VFNMADD132SD VEXVFNMADD132SD EVEXVFNMADD132SS VEXVFNMADD132SS EVEX	VFNMSUB132PD VEXVFNMSUB132PD EVEXVFNMSUB132PS VEXVFNMSUB132PS EVEX	VFNMSUB132SD VEXVFNMSUB132SD EVEXVFNMSUB132SS VEXVFNMSUB132SS EVEX
A									VFMADD132PD VEXVFMADD132PD EVEXVFMADD132PS VEXVFMADD132PS EVEX	VFMADD132SD VEXVFMADD132SD EVEXVFMADD132SS VEXVFMADD132SS EVEX	V4FMADDPS EVEXVFMSUB132PD VEXVFMSUB132PD EVEXVFMSUB132PS VEXVFMSUB132PS EVEX	V4FMADDSS EVEXVFMSUB132SD VEXVFMSUB132SD EVEXVFMSUB132SS VEXVFMSUB132SS EVEX	VFNMADD132PD VEXVFNMADD132PD EVEXVFNMADD132PS VEXVFNMADD132PS EVEX	VFNMADD132SD VEXVFNMADD132SD EVEXVFNMADD132SS VEXVFNMADD132SS EVEX	VFNMSUB132PD VEXVFNMSUB132PD EVEXVFNMSUB132PS VEXVFNMSUB132PS EVEX	VFNMSUB132SD VEXVFNMSUB132SD EVEXVFNMSUB132SS VEXVFNMSUB132SS EVEX
B	VCVTNEEBF162PS VEXVCVTNEEPH2PS VEXVCVTNEOBF162PS VEXVCVTNEOPH2PS VEX	VBCSTNEBF162PS VEXVBCSTNESH2PS VEX			VPMADD52LUQ VEXVPMADD52LUQ EVEX	VPMADD52HUQ VEXVPMADD52HUQ EVEX			VFMADD132PD VEXVFMADD132PD EVEXVFMADD132PS VEXVFMADD132PS EVEX	VFMADD132SD VEXVFMADD132SD EVEXVFMADD132SS VEXVFMADD132SS EVEX	VFMSUB132PD VEXVFMSUB132PD EVEXVFMSUB132PS VEXVFMSUB132PS EVEX	VFMSUB132SD VEXVFMSUB132SD EVEXVFMSUB132SS VEXVFMSUB132SS EVEX	VFNMADD132PD VEXVFNMADD132PD EVEXVFNMADD132PS VEXVFNMADD132PS EVEX	VFNMADD132SD VEXVFNMADD132SD EVEXVFNMADD132SS VEXVFNMADD132SS EVEX	VFNMSUB132PD VEXVFNMSUB132PD EVEXVFNMSUB132PS VEXVFNMSUB132PS EVEX	VFNMSUB132SD VEXVFNMSUB132SD EVEXVFNMSUB132SS VEXVFNMSUB132SS EVEX
C	TILERELEASE VEX				VPCONFLICTD EVEX				SHA1NEXTEVEXP2PD EVEXVEXP2PS EVEX	SHA1MSG1	SHA1MSG2VRCP28PD EVEXVRCP28PS EVEX	SHA256RNDS2VRCP28SD EVEXVRCP28SS EVEXVSHA512RNDS2 VEX	SHA256MSG1VRSQRT28PD EVEXVRSQRT28PS EVEXVSHA512MSG1 VEX	SHA256MSG2VRSQRT28SD EVEXVRSQRT28SS EVEXVSHA512MSG2 VEX		GF2P8MULB 66GF2P8MULB VEXGF2P8MULB EVEX
D			VPDPWSUD VEX	VPDPWSUD VEX					AESDECWIDE128KL F3AESDECWIDE256KL F3AESENCWIDE128KL F3AESENCWIDE256KL F3		VSM3MSG1 VEXVSM3MSG2 VEXVSM4KEY4 VEXVSM4RNDS4 VEX	AESIMC 66AESIMC VEX	AESENC 66AESENC VEXAESENC EVEXAESENC128KL F3LOADIWKEY F3	AESDEC128KL F3AESENCLAST 66AESENCLAST VEXAESENCLAST EVEX	AESDEC 66AESDEC VEXAESDEC EVEXAESENC256KL F3	AESDEC256KL F3AESDECLAST 66AESDECLAST VEXAESDECLAST EVEX
E	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX	CMPccXADD VEX
F	CRC32 F2MOVBE	CRC32 F2MOVBE				BZHI VEXPDEP VEXPEXT VEXWRUSSD 66	ADCX 66MULX VEXWRSSD	BEXTR VEXSARX VEX	ENQCMD F2ENQCMDS F3MOVDIR64B 66	MOVDIRI	ENCODEKEY128 F3	ENCODEKEY256 F3

Opcodes after 0F 3A

64 occupied cells, 133 encoding forms.

High	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	VPERMQ VEXVPERMQ EVEX	VPERMPD VEXVPERMPD EVEX	VPBLENDD VEX	VALIGND EVEX	VPERMILPS VEXVPERMILPS EVEX	VPERMILPD VEXVPERMILPD EVEX	VPERM2F128 VEX		ROUNDPS 66ROUNDPS VEXVRNDSCALEPH EVEXVRNDSCALEPS EVEX	ROUNDPD 66ROUNDPD VEXVRNDSCALEPD EVEX	ROUNDSS 66ROUNDSS VEXVRNDSCALESH EVEXVRNDSCALESS EVEX	ROUNDSD 66ROUNDSD VEXVRNDSCALESD EVEX	BLENDPS 66BLENDPS VEX	BLENDPD 66BLENDPD VEX	PBLENDW 66PBLENDW VEX	PALIGNRPALIGNR 66PALIGNR VEXPALIGNR EVEX
1					PEXTRB 66PEXTRB VEXPEXTRB EVEX	PEXTRW 66PEXTRW VEXPEXTRW EVEX	PEXTRB 66PEXTRB VEXPEXTRB EVEX	EXTRACTPS 66EXTRACTPS VEXEXTRACTPS EVEX						VCVTPS2PH VEXVCVTPS2PH EVEX	VPCMPD EVEXVPCMPQ EVEX	VPCMPD EVEXVPCMPQ EVEX
2	PINSRB 66PINSRB VEXPINSRB EVEX	INSERTPS 66INSERTPS VEXINSERTPS EVEX	PINSRB 66PINSRB VEXPINSRB EVEX			VPTERNLOGD EVEX	VGETMANTPD EVEXVGETMANTPH EVEXVGETMANTPS EVEX	VGETMANTSD EVEXVGETMANTSH EVEXVGETMANTSS EVEX
3	KSHIFTRW VEX	KSHIFTRW VEX	KSHIFTLW VEX	KSHIFTLW VEX											VPCMPB EVEXVPCMPW EVEX	VPCMPB EVEXVPCMPW EVEX
4	DPPS 66DPPS VEX	DPPD 66DPPD VEX	MPSADBW 66MPSADBW VEXVDBPSADBW EVEX		PCLMULQDQ 66PCLMULQDQ VEXPCLMULQDQ EVEX		VPERM2I128 VEX				BLENDVPS VEX	BLENDVPD VEX	PBLENDVB VEX
5	VRANGEPD EVEXVRANGEPS EVEX	VRANGESD EVEXVRANGESS EVEX			VFIXUPIMMPD EVEXVFIXUPIMMPS EVEX	VFIXUPIMMSD EVEXVFIXUPIMMSS EVEX	VREDUCEPD EVEXVREDUCEPH EVEXVREDUCEPS EVEX	VREDUCESD EVEXVREDUCESH EVEXVREDUCESS EVEX
6	PCMPESTRM 66PCMPESTRM VEX	PCMPESTRI 66PCMPESTRI VEX	PCMPISTRM 66PCMPISTRM VEX	PCMPISTRI 66PCMPISTRI VEX				VFPCLASSSD EVEXVFPCLASSSH EVEXVFPCLASSSS EVEX
7	VPSHLD EVEX	VPSHLD EVEX	VPSHRD EVEX	VPSHRD EVEX
8
9
A
B
C			VCMPPH EVEXVCMPSH EVEX										SHA1RNDS4		GF2P8AFFINEQB 66GF2P8AFFINEQB VEXGF2P8AFFINEQB EVEX	GF2P8AFFINEINVQB 66GF2P8AFFINEINVQB VEXGF2P8AFFINEINVQB EVEX
D															VSM3RNDS2 VEX	AESKEYGENASSIST 66AESKEYGENASSIST VEX
E
F	HRESET F3

Opcodes after MAP5

25 occupied cells, 50 encoding forms.

High	0	1	8	9	A	B	C	D	E	F
0
1	VMOVSH EVEX	VMOVSH EVEX						VCVTPS2PHX EVEXVCVTSS2SH EVEX
2					VCVTSI2SH EVEX		VCVTTSH2SI EVEX	VCVTSH2SI EVEX	VUCOMISH EVEX	VCOMISH EVEX
3
4
5		VSQRTPH EVEXVSQRTSH EVEX	VADDPH EVEXVADDSH EVEX	VMULPH EVEXVMULSH EVEX	VCVTPD2PH EVEXVCVTPH2PD EVEXVCVTSD2SH EVEXVCVTSH2SD EVEX	VCVTDQ2PH EVEXVCVTPH2DQ EVEXVCVTQQ2PH EVEXVCVTTPH2DQ EVEX	VSUBPH EVEXVSUBSH EVEX	VMINPH EVEXVMINSH EVEX	VDIVPH EVEXVDIVSH EVEX	VMAXPH EVEXVMAXSH EVEX
6									VMOVW EVEX
7			VCVTTPH2UDQ EVEXVCVTTPH2UQQ EVEXVCVTTSH2USI EVEX	VCVTPH2UDQ EVEXVCVTPH2UQQ EVEXVCVTSH2USI EVEX	VCVTTPH2QQ EVEXVCVTUDQ2PH EVEXVCVTUQQ2PH EVEX	VCVTPH2QQ EVEXVCVTUSI2SH EVEX	VCVTTPH2UW EVEXVCVTTPH2W EVEX	VCVTPH2UW EVEXVCVTPH2W EVEXVCVTUW2PH EVEXVCVTW2PH EVEX	VMOVW EVEX
8
9
A
B
C
D
E
F

Opcodes after MAP6

37 occupied cells, 38 encoding forms.

High	2	3	6	7	8	9	A	B	C	D	E	F
0
1		VCVTPH2PS EVEXVCVTSH2SS EVEX
2									VSCALEFPH EVEX	VSCALEFSH EVEX
3
4	VGETEXPPH EVEX	VGETEXPSH EVEX							VRCPPH EVEX	VRCPSH EVEX	VRSQRTPH EVEX	VRSQRTSH EVEX
5			VFCMADDCPH EVEX	VFCMADDCSH EVEX
6
7
8
9					VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX	VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX
A					VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX	VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX
B					VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX	VFMADD132PH EVEX	VFMADD132SH EVEX	VFMSUB132PH EVEX	VFMSUB132SH EVEX
C
D			VFCMULCPH EVEX	VFCMULCSH EVEX
E
F