PXOR

Logical Exclusive OR

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`NP 0F EF /r1`	`PXOR mm, mm/m64`	A	Valid	Valid	Bitwise XOR of mm/m64 and mm.
`66 0F EF /r`	`PXOR xmm1, xmm2/m128`	A	Valid	Valid	Bitwise XOR of xmm2/m128 and xmm1.
`VEX.128.66.0F.WIG EF /r`	`VPXOR xmm1, xmm2, xmm3/m128`	B	Valid	Valid	Bitwise XOR of xmm3/m128 and xmm2.
`VEX.256.66.0F.WIG EF /r`	`VPXOR ymm1, ymm2, ymm3/m256`	B	Valid	Valid	Bitwise XOR of ymm3/m256 and ymm2.
`EVEX.128.66.0F.W0 EF /r`	`VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst`	C	Valid	Valid	Bitwise XOR of packed doubleword integers in AVX512F) OR xmm2 and xmm3/m128 using writemask k1. AVX10.1
`EVEX.256.66.0F.W0 EF /r`	`VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst`	C	Valid	Valid	Bitwise XOR of packed doubleword integers in AVX512F) OR ymm2 and ymm3/m256 using writemask k1. AVX10.1
`EVEX.512.66.0F.W0 EF /r`	`VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst`	C	Valid	Valid	Bitwise XOR of packed doubleword integers in OR AVX10.1 zmm2 and zmm3/m512/m32bcst using writemask k1.
`EVEX.128.66.0F.W1 EF /r`	`VPXORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst`	C	Valid	Valid	Bitwise XOR of packed quadword integers in AVX512F) OR xmm2 and xmm3/m128 using writemask k1. AVX10.1
`EVEX.256.66.0F.W1 EF /r`	`VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst`	C	Valid	Valid	Bitwise XOR of packed quadword integers in AVX512F) OR ymm2 and ymm3/m256 using writemask k1. AVX10.1
`EVEX.512.66.0F.W1 EF /r`	`VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst`	C	Valid	Valid	Bitwise XOR of packed quadword integers in OR AVX10.1 zmm2 and zmm3/m512/m64bcst using writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

B

modrm.reg escrituraModRM byte, reg field (bits 5-3)
vex.vvvv lecturaVEX prefix, vvvv field (inverted)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

C

modrm.reg escrituraModRM byte, reg field (bits 5-3)
evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corresponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Operation

PXOR (64-bit Operand)
DEST := DEST XOR SRC

PXOR (128-bit Legacy SSE Version)
DEST := DEST XOR SRC
DEST[MAXVL-1:128] (Unmodified)

VPXOR (VEX.128 Encoded Version)
DEST := SRC1 XOR SRC2
DEST[MAXVL-1:128] := 0

VPXOR (VEX.256 Encoded Version)
DEST := SRC1 XOR SRC2
DEST[MAXVL-1:256] := 0

VPXORD (EVEX Encoded Versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                  THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[31:0]

                  ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]

             FI;

ELSE

     IF *merging-masking*                 ; merging-masking

             THEN *DEST[31:0] remains unchanged*

             ELSE                         ; zeroing-masking

                  DEST[31:0] := 0

     FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0


VPXORQ (EVEX Encoded Versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                  THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[63:0]

                  ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]

             FI;

ELSE

     IF *merging-masking*                ; merging-masking

             THEN *DEST[63:0] remains unchanged*

             ELSE                        ; zeroing-masking

                  DEST[63:0] := 0

     FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b) VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b) VPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b) VPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b) VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b) VPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b) VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b) VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b) VPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b) VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);
VPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);
VPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);
VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);
VPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);
VPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);
VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);
VPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);
VPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);
PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2) (V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b) VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b);

Flags affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, "Type 4 Class Exception Conditions." EVEX-encoded instruction, see Table 2-51, "Type E4 Class Exception Conditions."

PXOR

Encodings

Operand encoding

A

B

C

Measured cost

Description#

Operation#

Intel C/C++ compiler intrinsics#

Flags affected#

Numeric Exceptions#