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Source code

TPAUSE

Timed PAUSE

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F AE /6TPAUSE r32, <edx>, <eax> Op/En Tuple A N/AAValidValidDirects the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Inst ruction O perand Encoding1 Operand 1 Ope rand 2 Operand 3 Operand 4 ModRM:r/ m (r) N/A N/A N/A

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

TPAUSE instructs the processor to enter an implementation-dependent optimized state. There are two such optimized states to choose from: light-weight power/performance optimized state, and improved power/performance optimized state. The selection between the two is governed by the explicit input register bit[0] source operand.

TPAUSE is available when CPUID.07H.00H:ECX.WAITPKG[5] is enumerated as 1. TPAUSE may be executed at any privilege level. This instruction's operation is the same in non-64-bit modes and in 64-bit mode.

Unlike PAUSE, the TPAUSE instruction will not cause an abort when used inside a transactional region, described in the chapter Chapter 16, "Programming with Intel(R) AVX10," of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1.

The input register contains information such as the preferred optimized state the processor should enter as described in the following table. Bits other than bit 0 are reserved and will result in #GP if non-zero.

TPAUSE Input Register Bit Definitions

Bit ValueState NameWakeup TimePower SavingsOther Benefits
bit[0] = 0C0.2SlowerLargerImproves performance of the other SMT thread(s) on the same core.
bit[0] = 1C0.1FasterSmallerN/A
bits[31:1]N/AN/AN/AReserved

Operation

os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2)
instr_deadline := UINT64(EDX:EAX)

IF os_deadline < instr_deadline:
    deadline := os_deadline
    using_os_deadline := 1

ELSE:
    deadline := instr_deadline
    using_os_deadline := 0

WHILE TSC < deadline:
    implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0])

IF using_os_deadline AND TSC  deadline:
    RFLAGS.CF := 1

ELSE:
    RFLAGS.CF := 0

RFLAGS.AF,PF,SF,ZF,OF := 0

Intel C/C++ compiler intrinsics

TPAUSE uint8_t _tpause(uint32_t control, uint64_t counter);

Numeric Exceptions

None.

Exceptions

Real address mode
#GP(0)If src[31:1] != 0. If CR4.TSD = 1 and CPL != 0.
#UDIf CPUID.07H.00H:ECX.WAITPKG[5]=0.
Protected mode
#GP(0)If src[31:1] != 0. If CR4.TSD = 1 and CPL != 0.
#UDIf CPUID.07H.00H:ECX.WAITPKG[5]=0.
Virtual-8086 mode
#GP(0)If src[31:1] != 0. If CR4.TSD = 1 and CPL != 0.
#UDIf CPUID.07H.00H:ECX.WAITPKG[5]=0.
Compatibility mode
#GP(0)If src[31:1] != 0. If CR4.TSD = 1 and CPL != 0.
#UDIf CPUID.07H.00H:ECX.WAITPKG[5]=0.
64-bit mode
#GP(0)If src[31:1] != 0. If CR4.TSD = 1 and CPL != 0.
#UDIf CPUID.07H.00H:ECX.WAITPKG[5]=0.

Sources