UD

Undefined Instruction

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`0F FF /r`	`UD01 r32, r/m32`	RM	Valid	Valid	Raise invalid opcode exception.
`0F B9 /r`	`UD1 r32, r/m32`	RM	Valid	Valid	Raise invalid opcode exception.
`0F 0B`	`UD2`	ZO	Valid	Valid	Raise invalid opcode exception.
`D6`	`UDB`	ZO	Valid	Not encodable	Raise invalid opcode exception.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

modrm.reg lecturaModRM byte, reg field (bits 5-3)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Not measured: it does not run on 64-bit processors.

Description

Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an invalid opcode exception. The opcodes for this instruction are reserved for this purpose. Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory. Even though it is the execution of the UD instruction that causes the invalid opcode exception, the instruction pointer saved by delivery of the exception references the UD instruction (and not the following instruction). This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation

#UD (* Generates invalid opcode exception *);