CMPccXADD
Compare and Add if Condition is Met
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
VEX.128.66.0F38.W0 E6 !(11):rrr:bbb | CMPBEXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If below or equal (CF=1 or ZF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E6 !(11):rrr:bbb | CMPBEXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If below or equal (CF=1 or ZF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E2 !(11):rrr:bbb | CMPBXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If below (CF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E2 !(11):rrr:bbb | CMPBXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If below (CF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 EE !(11):rrr:bbb | CMPLEXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If less or equal (ZF=1 or SFOF), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 EE !(11):rrr:bbb | CMPLEXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If less or equal (ZF=1 or SFOF), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 EC !(11):rrr:bbb | CMPLXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If less (SFOF), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 EC !(11):rrr:bbb | CMPLXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If less (SFOF), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E7 !(11):rrr:bbb | CMPNBEXADD m32, r32, r32 Opcode/ Instruction | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not below or equal (CF=0 and ZF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. O p/ 64/32 bit CPUID Feature Description E n Mode Support Flag |
VEX.128.66.0F38.W1 E7 !(11):rrr:bbb | CMPNBEXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not below or equal (CF=0 and ZF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E3 !(11):rrr:bbb | CMPNBXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not below (CF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E3 !(11):rrr:bbb | CMPNBXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not below (CF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 EF !(11):rrr:bbb | CMPNLEXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not less or equal (ZF=0 and SF=OF), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 EF !(11):rrr:bbb | CMPNLEXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not less or equal (ZF=0 and SF=OF), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 ED !(11):rrr:bbb | CMPNLXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not less (SF=OF), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 ED !(11):rrr:bbb | CMPNLXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not less (SF=OF), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E1 !(11):rrr:bbb | CMPNOXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not overflow (OF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E1 !(11):rrr:bbb | CMPNOXADD m64, r64, r64 Opcode/ Instruction | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not overflow (OF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. O p/ 64/32 bit CPUID Feature Description E n Mode Support Flag |
VEX.128.66.0F38.W0 EB !(11):rrr:bbb | CMPNPXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not parity (PF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 EB !(11):rrr:bbb | CMPNPXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not parity (PF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E9 !(11):rrr:bbb | CMPNSXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not sign (SF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E9 !(11):rrr:bbb | CMPNSXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not sign (SF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E5 !(11):rrr:bbb | CMPNZXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If not zero (ZF=0), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E5 !(11):rrr:bbb | CMPNZXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If not zero (ZF=0), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E0 !(11):rrr:bbb | CMPOXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If overflow (OF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E0 !(11):rrr:bbb | CMPOXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If overflow (OF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 EA !(11):rrr:bbb | CMPPXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If parity (PF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 EA !(11):rrr:bbb | CMPPXADD m64, r64, r64 Opcode/ Instruction | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If parity (PF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. O p/ 64/32 bit CPUID Feature Description E n Mode Support Flag |
VEX.128.66.0F38.W0 E8 !(11):rrr:bbb | CMPSXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If sign (SF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E8 !(11):rrr:bbb | CMPSXADD m64, r64, r64 | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If sign (SF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. |
VEX.128.66.0F38.W0 E4 !(11):rrr:bbb | CMPZXADD m32, r32, r32 | A | Valid | Not encodable | Compare value in r32 (second operand) with value in m32. If zero (ZF=1), add value from r32 (third operand) to m32 and write new value in m32. The second operand is always updated with the original value from m32. |
VEX.128.66.0F38.W1 E4 !(11):rrr:bbb | CMPZXADD m64, r64, r64 Op/En Tuple Type Operand 1 A N/A ModRM:r/m (r, | A | Valid | Not encodable | Compare value in r64 (second operand) with value in m64. If zero (ZF=1), add value from r64 (third operand) to m64 and write new value in m64. The second operand is always updated with the original value from m64. Instructio n Operand Encod ing1 Op erand 2 Operand 3 Operand 4 w) ModRM:reg (r, w) VEX.vvvv (r) N/A |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
A
modrm.rmlectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for themmodrm.reglectura y escrituraModRM byte, reg field (bits 5-3)vex.vvvvlecturaVEX prefix, vvvv field (inverted)
Measured cost
Not measured: it does not run on 64-bit processors.
Description
This instruction compares the value from memory with the value of the second operand. If the specified condition is met, then the processor will add the third operand to the memory operand and write it into memory, else the memory is unchanged by this instruction.
This instruction must have MODRM.MOD equal to 0, 1, or 2. The value 3 for MODRM.MOD is reserved and will cause an invalid opcode exception (#UD).
The second operand is always updated with the original value of the memory operand. The EFLAGS conditions are updated from the results of the comparison.The instruction uses an implicit lock. This instruction does not permit the use of an explicit lock prefix.
Operation
CMPCCXADD srcdest1, srcdest2, src3
tmp1 := load lock srcdest1
tmp2 := tmp1 + src3
EFLAGS.CS,OF,SF,ZF,AF,PF := CMP tmp1, srcdest2
IF <condition>:
srcdest1 := store unlock tmp2
ELSE
srcdest1 := store unlock tmp1
srcdest2 :=tmp1
1. ModRM.MOD != 011BFlags affected
The EFLAGS conditions are updated from the results of the comparison.
Intel C/C++ compiler intrinsics
CMPCCXADD int _cmpccxadd_epi32 (void* __A, int __B, int __C, const int __D);
CMPCCXADD __int64 _cmpccxadd_epi64 (void* __A, __int64 __B, __int64 __C, const int __D);SIMD Floating-Point Exceptions
None.
Exceptions Exceptions Type 14; see Table 2-31.