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VSCALEFPD

Scale Packed Float64 Values With Float64 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W1 2C /rVSCALEFPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstAValidValidScale the packed double precision floating-point AND AVX512F) values in xmm2 using values from OR AVX10.1 xmm3/m128/m64bcst. Under writemask k1.
EVEX.256.66.0F38.W1 2C /rVSCALEFPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstAValidValidScale the packed double precision floating-point AND AVX512F) values in ymm2 using values from OR AVX10.1 ymm3/m256/m64bcst. Under writemask k1.
EVEX.512.66.0F38.W1 2C /rVSCALEFPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}AValidValidScale the packed double precision floating-point OR AVX10.1 values in zmm2 using values from zmm3/m512/m64bcst. Under writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

Performs a floating-point scale of the packed double precision floating-point values in the first source operand by multiplying them by 2 to the power of the double precision floating-point values in second source operand.

The equation of this operation is given by:

zmm1 := zmm2*2floor(zmm3).

Floor(zmm3) means maximum integer value zmm3.

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-37 and Table 5-38.

VSCALEFPD/SD/PS/SS Special Cases

Src1+/-QNaNQNaN(Src1)+INF+0QNaN(Src1)IF either source is SNAN
+/-SNaNQNaN(Src1)QNaN(Src1)QNaN(Src1)QNaN(Src1)YES
+/-InfQNaN(Src2)Src1QNaN_IndefiniteSrc1IF Src2 is SNAN or -INF
+/-0QNaN(Src2)QNaN_IndefiniteSrc1Src1IF Src2 is SNAN or +INF

Operation

SCALE(SRC1, SRC2)

{

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 64 bits floating-point value */

DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))

}

VSCALEFPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)

     THEN

           SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

     ELSE

           SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

     i := j * 64

     IF k1[j] OR *no writemask* THEN

                  IF (EVEX.b = 1) AND (SRC2 *is memory*)

                       THEN DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[63:0]);

                       ELSE DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[i+63:i]);

                  FI;

           ELSE

                  IF *merging-masking*        ; merging-masking

                       THEN *DEST[i+63:i] remains unchanged*

                       ELSE                   ; zeroing-masking

                       DEST[i+63:i] := 0

                  FI

     FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VSCALEFPD __m512d _mm512_scalef_round_pd(__m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_mask_scalef_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_maskz_scalef_round_pd(__mmask8 k, __m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_scalef_pd(__m512d a, __m512d b);
VSCALEFPD __m512d _mm512_mask_scalef_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VSCALEFPD __m512d _mm512_maskz_scalef_pd(__mmask8 k, __m512d a, __m512d b);
VSCALEFPD __m256d _mm256_scalef_pd(__m256d a, __m256d b);
VSCALEFPD __m256d _mm256_mask_scalef_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VSCALEFPD __m256d _mm256_maskz_scalef_pd(__mmask8 k, __m256d a, __m256d b);
VSCALEFPD __m128d _mm_scalef_pd(__m128d a, __m128d b);
VSCALEFPD __m128d _mm_mask_scalef_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VSCALEFPD __m128d _mm_maskz_scalef_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal (for Src1).

Denormal is not reported for Src2.

Other Exceptions

See Table 2-48, "Type E2 Class Exception Conditions."

Sources