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Source code

KMOVW, KMOVB, KMOVQ, KMOVD

Move From and to Mask Registers

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.L0.0F.W0 90 /rKMOVW k1, k2/m16RMValidValidMove 16 bits mask from k2/m16 and store the result in k1. OR AVX10.1
VEX.L0.66.0F.W0 90 /rKMOVB k1, k2/m8RMValidValidMove 8 bits mask from k2/m8 and store the result in k1. OR AVX10.1
VEX.L0.0F.W1 90 /rKMOVQ k1, k2/m64RMValidValidMove 64 bits mask from k2/m64 and store the result in k1. OR AVX10.1
VEX.L0.66.0F.W1 90 /rKMOVD k1, k2/m32RMValidValidMove 32 bits mask from k2/m32 and store the result in k1. OR AVX10.1
VEX.L0.0F.W0 91 /rKMOVW m16, k1MRValidValidMove 16 bits mask from k1 and store the result in m16. OR AVX10.1
VEX.L0.66.0F.W0 91 /rKMOVB m8, k1MRValidValidMove 8 bits mask from k1 and store the result in m8. OR AVX10.1
VEX.L0.0F.W1 91 /rKMOVQ m64, k1MRValidValidMove 64 bits mask from k1 and store the result in m64. OR AVX10.1
VEX.L0.66.0F.W1 91 /rKMOVD m32, k1MRValidValidMove 32 bits mask from k1 and store the result in m32. OR AVX10.1
VEX.L0.0F.W0 92 /rKMOVW k1, r32RRValidValidMove 16 bits mask from r32 to k1. OR AVX10.1
VEX.L0.66.0F.W0 92 /rKMOVB k1, r32RRValidValidMove 8 bits mask from r32 to k1. OR AVX10.1
VEX.L0.F2.0F.W1 92 /rKMOVQ k1, r64RRValidInvalidMove 64 bits mask from r64 to k1. OR AVX10.1
VEX.L0.F2.0F.W0 92 /rKMOVD k1, r32RRValidValidMove 32 bits mask from r32 to k1. OR AVX10.1
VEX.L0.0F.W0 93 /rKMOVW r32, k1RRValidValidMove 16 bits mask from k1 to r32. OR AVX10.1
VEX.L0.66.0F.W0 93 /rKMOVB r32, k1RRValidValidMove 8 bits mask from k1 to r32. OR AVX10.1
VEX.L0.F2.0F.W1 93 /rKMOVQ r64, k1RRValidInvalidMove 64 bits mask from k1 to r64. OR AVX10.1
VEX.L0.F2.0F.W0 93 /rKMOVD r32, k1RRValidValidMove 32 bits mask from k1 to r32. OR AVX10.1

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

MR

  1. modrm.rm lectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. modrm.reg lecturaModRM byte, reg field (bits 5-3)

RR

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Copies values from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be mask registers, memory location or general purpose. The instruction cannot be used to transfer data between general purpose registers and or memory locations.

When moving to a mask register, the result is zero extended to MAX_KL size (i.e., 64 bits currently). When moving to a general-purpose register (GPR), the result is zero-extended to the size of the destination. In 32-bit mode, the default GPR destination's size is 32 bits. In 64-bit mode, the default GPR destination's size is 64 bits. Note that VEX.W can only be used to modify the size of the GPR operand in 64b mode.

Operation

KMOVW
IF *destination is a memory location*

    DEST[15:0] := SRC[15:0]
IF *destination is a mask register or a GPR *

    DEST := ZeroExtension(SRC[15:0])

KMOVB
IF *destination is a memory location*

    DEST[7:0] := SRC[7:0]
IF *destination is a mask register or a GPR *

    DEST := ZeroExtension(SRC[7:0])

KMOVQ
IF *destination is a memory location or a GPR*

    DEST[63:0] := SRC[63:0]
IF *destination is a mask register*

    DEST := ZeroExtension(SRC[63:0])

KMOVD
IF *destination is a memory location*

    DEST[31:0] := SRC[31:0]
IF *destination is a mask register or a GPR *

    DEST := ZeroExtension(SRC[31:0])

Intel C/C++ compiler intrinsics

KMOVW __mmask16 _mm512_kmov(__mmask16 a);

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Instructions with RR operand encoding, see Table 2-65, "TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)." Instructions with RM or MR operand encoding, see Table 2-66, "TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory)."

Sources