Vesta
English
Source code

VMOVSH

Move Scalar FP16 Value

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.LLIG.F3.MAP5.W0 10 /rVMOVSH xmm1{k1}{z}, m16AValidValidMove FP16 value from m16 to xmm1 subject to OR AVX10.1 writemask k1.
EVEX.LLIG.F3.MAP5.W0 11 /rVMOVSH m16{k1}, xmm1BValidValidMove low FP16 value from xmm1 to m16 subject OR AVX10.1 to writemask k1.
EVEX.LLIG.F3.MAP5.W0 10 /rVMOVSH xmm1{k1}{z}, xmm2, xmm3CValidValidMove low FP16 values from xmm3 to xmm1 OR AVX10.1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].
EVEX.LLIG.F3.MAP5.W0 11 /rVMOVSH xmm1{k1}{z}, xmm2, xmm3DValidValidMove low FP16 values from xmm3 to xmm1 OR AVX10.1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Scalar

B

  1. modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. modrm.reg lecturaModRM byte, reg field (bits 5-3)

Tupla: Scalar

C

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

D

  1. modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.reg lecturaModRM byte, reg field (bits 5-3)

Measured cost

Loading measurements from arch-data...

Description

This instruction moves a FP16 value to a register or memory location.

The two register-only forms are aliases and differ only in where their operands are encoded; this is a side effect of the encodings selected.

Operation

VMOVSH dest, src (two operand load)
IF k1[0] or no writemask:

    DEST.fp16[0] := SRC.fp16[0]
ELSE IF *zeroing*:

    DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged

DEST[MAXVL:16] := 0

VMOVSH dest, src (two operand store)
IF k1[0] or no writemask:

    DEST.fp16[0] := SRC.fp16[0]
// ELSE DEST.fp16[0] remains unchanged


VMOVSH dest, src1, src2 (three operand copy)
IF k1[0] or no writemask:

    DEST.fp16[0] := SRC2.fp16[0]
ELSE IF *zeroing*:

    DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]
DEST[MAXVL:128] := 0

Intel C/C++ compiler intrinsics

VMOVSH __m128h _mm_load_sh (void const* mem_addr);
VMOVSH __m128h _mm_mask_load_sh (__m128h src, __mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_maskz_load_sh (__mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_mask_move_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_maskz_move_sh (__mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_move_sh (__m128h a, __m128h b);
VMOVSH void _mm_mask_store_sh (void * mem_addr, __mmask8 k, __m128h a);
VMOVSH void _mm_store_sh (void * mem_addr, __m128h a);

SIMD Floating-Point Exceptions

None

Other Exceptions

EVEX-encoded instruction, see Table 2-53, "Type E5 Class Exception Conditions."

Sources