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Source code

FSUB, FSUBP, FISUB

Subtract

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
D8 /4FSUB m32fpValidValidSubtract m32fp from ST(0) and store result in ST(0).
DC /4FSUB m64fpValidValidSubtract m64fp from ST(0) and store result in ST(0).
D8 E0+iFSUB ST(0), ST(i)ValidValidSubtract ST(i) from ST(0) and store result in ST(0).
DC E8+iFSUB ST(i), ST(0)ValidValidSubtract ST(0) from ST(i) and store result in ST(i).
DE E8+iFSUBP ST(i), ST(0)ValidValidSubtract ST(0) from ST(i), store result in ST(i), and pop register stack.
DE E9FSUBPValidValidSubtract ST(0) from ST(1), store result in ST(1), and pop register stack.
DA /4FISUB m32intValidValidSubtract m32int from ST(0) and store result in ST(0).
DE /4FISUB m16intValidValidSubtract m16int from ST(0) and store result in ST(0).

Measured cost

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Description

Subtracts the source operand from the destination operand and stores the difference in the destination location. The destination operand is always an FPU data register; the source operand can be a register or a memory location. Source operands in memory can be in single precision or double precision floating-point format or in word or doubleword integer format.

The no-operand version of the instruction subtracts the contents of the ST(0) register from the ST(1) register and stores the result in ST(1). The one-operand version subtracts the contents of a memory location (either a floatingpoint or an integer value) from the contents of the ST(0) register and stores the result in ST(0). The two-operand version, subtracts the contents of the ST(0) register from the ST(i) register or vice versa.

The FSUBP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUB rather than FSUBP.

The FISUB instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.

Table 3-40 shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST - SRC = result).

When the difference between two operands of like sign is 0, the result is +0, except for the round toward - mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the source operand is an integer 0, it is treated as a +0.

When one operand is , the result is of the expected sign. If both operands are of the same sign, an invalidoperation exception is generated.

FSUB/FSUBP/FISUB Results

-*-----NaN
-F ++/-F or +/-0DESTDEST -F-NaN
-0 +-SRC+/-0-0- SRC-NaN
+0 +-SRC+0+/-0- SRC-NaN
+F ++FDESTDEST+/-F or +/-0-NaN
+ +++++*NaN
NaN NaNNaNNaNNaNNaNNaNNaN

Operation

IF Instruction = FISUB
    THEN

        DEST := DEST - ConvertToDoubleExtendedPrecisionFP(SRC);

    ELSE (* Source operand is floating-point value *)

        DEST := DEST - SRC;

FI;

IF Instruction = FSUBP
    THEN
          PopRegisterStack;

FI;

FPU Flags Affected

C1                  Set to 0 if stack underflow occurred.

                    Set if result was rounded up; cleared otherwise.

C0, C2, C3          Undefined.

Floating-Point Exceptions

#IS                 Stack underflow occurred.
#IA                 Operand is an SNaN value or unsupported format.

Operands are infinities of like sign.

#D                  Source operand is a denormal value.
#U                  Result is too small for destination format.
#O                  Result is too large for destination format.
#P                  Value cannot be represented exactly in destination format.

Exceptions

Protected mode
#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
#SS(0)If a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used.
Real address mode
#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SSIf a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
Virtual-8086 mode
#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)If a memory operand effective address is outside the SS segment limit.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made.
#UDIf the LOCK prefix is used.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
#SS(0)If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)If the memory address is in a non-canonical form.
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used.

Sources