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Source code

OUT

Output to Port

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
E6 ibOUT imm8, ALIValidValidOutput byte in AL to I/O port address imm8.
E7 ibOUT imm8, AXIValidValidOutput word in AX to I/O port address imm8.
E7 ibOUT imm8, EAXIValidValidOutput doubleword in EAX to I/O port address imm8.
EEOUT DX, ALZOValidValidOutput byte in AL to I/O port address in DX.
EFOUT DX, AXZOValidValidOutput word in AX to I/O port address in DX.
EFOUT DX, EAXZOValidValidOutput doubleword in EAX to I/O port address in DX.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

I

  1. imm8immediate byte after the instruction

Measured cost

Loading measurements from arch-data...

Description

Copies the value from the second operand (source operand) to the I/O port specified with the destination operand (first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register. Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16-or 32-bit I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 20, "Input/Output," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 architecture compatibility

After executing an OUT instruction, the Pentium(R) processor ensures that the EWBE# pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the EWBE# pin.

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
    THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
         IF (Any I/O Permission Bit for I/O port being accessed = 1)
                THEN (* I/O operation is not allowed *)
                      #GP(0);
                ELSE ( * I/O operation is allowed *)
                      DEST := SRC; (* Writes to selected I/O port *)
          FI;
    ELSE (Real Mode or Protected Mode with CPL  IOPL *)
          DEST := SRC; (* Writes to selected I/O port *)

FI;

Flags affected

None.

Exceptions

Protected mode
#GP(0)If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
#UDIf the LOCK prefix is used.
Real address mode
#UDIf the LOCK prefix is used.
Virtual-8086 mode
#GP(0)If any of the I/O permission bits in the TSS for the I/O port being accessed is 1. #PF(fault-code) If a page fault occurs.
#UDIf the LOCK prefix is used.
Compatibility mode
Same as protected mode exceptions.
64-bit mode
Same as protected mode exceptions.

Sources