AND
Logical AND
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
24 ib | AND AL, imm8 | I | Valid | Valid | AL AND imm8. |
25 iw | AND AX, imm16 | I | Valid | Valid | AX AND imm16. |
25 id | AND EAX, imm32 | I | Valid | Valid | EAX AND imm32. |
REX.W + 25 id | AND RAX, imm32 | I | Valid | Not encodable | RAX AND imm32 sign-extended to 64-bits. |
80 /4 ib | AND r/m8, imm8 | MI | Valid | Valid | r/m8 AND imm8. |
81 /4 iw | AND r/m16, imm16 | MI | Valid | Valid | r/m16 AND imm16. |
81 /4 id | AND r/m32, imm32 | MI | Valid | Valid | r/m32 AND imm32. |
REX.W + 81 /4 id | AND r/m64, imm32 | MI | Valid | Not encodable | r/m64 AND imm32 sign extended to 64-bits. |
83 /4 ib | AND r/m16, imm8 | MI | Valid | Valid | r/m16 AND imm8 (sign-extended). |
83 /4 ib | AND r/m32, imm8 | MI | Valid | Valid | r/m32 AND imm8 (sign-extended). |
REX.W + 83 /4 ib | AND r/m64, imm8 | MI | Valid | Not encodable | r/m64 AND imm8 (sign-extended). |
20 /r | AND r/m8, r8 | MR | Valid | Valid | r/m8 AND r8. |
21 /r | AND r/m16, r16 | MR | Valid | Valid | r/m16 AND r16. |
21 /r | AND r/m32, r32 | MR | Valid | Valid | r/m32 AND r32. |
REX.W + 21 /r | AND r/m64, r64 | MR | Valid | Not encodable | r/m64 AND r64. |
22 /r | AND r8, r/m8 | RM | Valid | Valid | r8 AND r/m8. |
23 /r | AND r16, r/m16 | RM | Valid | Valid | r16 AND r/m16. |
23 /r | AND r32, r/m32 | RM | Valid | Valid | r32 AND r/m32. |
REX.W + 23 /r | AND r64, r/m64 | RM | Valid | Not encodable | r64 AND r/m64. |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RM
modrm.reglectura y escrituraModRM byte, reg field (bits 5-3)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
MR
modrm.rmlectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for themmodrm.reglecturaModRM byte, reg field (bits 5-3)
MI
modrm.rmlectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for themimm8/16/32immediate after the instruction, as wide as the operand
I
AL/AX/EAX/RAXimm8/16/32immediate after the instruction, as wide as the operand
Measured cost
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Flags named
CFCarryPFParityAFAuxiliary carryZFZeroSFSignOFOverflow
Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
This instruction can be used with a LOCK prefix to allow the it to be executed atomically.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST := DEST AND SRC;Flags affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
Exceptions
Protected mode
#GP(0) | If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Real address mode
#GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS | If a memory operand effective address is outside the SS segment limit. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Virtual-8086 mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |
Compatibility mode
| Same exceptions as in protected mode. |
64-bit mode
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
#GP(0) | If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used but the destination is not a memory operand. |