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Source code

STMXCSR

Store MXCSR Register State

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
NP 0F AE /3STMXCSR m32MValidValidStore contents of MXCSR register to m32.
VEX.LZ.0F.WIG AE /3VSTMXCSR m32MValidValidStore contents of MXCSR register to m32.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

M

  1. modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s. This instruction's operation is the same in non-64-bit modes and 64-bit mode. VEX.L must be 0, otherwise instructions will #UD. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

m32 := MXCSR;

Intel C/C++ compiler intrinsics

_mm_getcsr(void);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-22, "Type 5 Class Exception Conditions," additionally:

#UD                  If VEX.L= 1,
                     If VEX.vvvv  1111B.

Sources