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Source code

VFMADD132PH, VFMADD213PH, VFMADD231PH, VFNMADD132PH, VFNMADD213PH, VFNMADD231PH

Fused Multiply-Add of Packed FP16 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.MAP6.W0 98 /rVFMADD132PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidMultiply packed FP16 values from xmm1 and AND AVX512VL) xmm3/m128/m16bcst, add to xmm2, and store OR AVX10.1 the result in xmm1.
EVEX.256.66.MAP6.W0 98 /rVFMADD132PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidMultiply packed FP16 values from ymm1 and AND AVX512VL) ymm3/m256/m16bcst, add to ymm2, and store OR AVX10.1 the result in ymm1.
EVEX.512.66.MAP6.W0 98 /rVFMADD132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidMultiply packed FP16 values from zmm1 and OR AVX10.1 zmm3/m512/m16bcst, add to zmm2, and store the result in zmm1.
EVEX.128.66.MAP6.W0 A8 /rVFMADD213PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidMultiply packed FP16 values from xmm1 and AND AVX512VL) xmm2, add to xmm3/m128/m16bcst, and store OR AVX10.1 the result in xmm1.
EVEX.256.66.MAP6.W0 A8 /rVFMADD213PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidMultiply packed FP16 values from ymm1 and AND AVX512VL) ymm2, add to ymm3/m256/m16bcst, and store OR AVX10.1 the result in ymm1.
EVEX.512.66.MAP6.W0 A8 /rVFMADD213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidMultiply packed FP16 values from zmm1 and OR AVX10.1 zmm2, add to zmm3/m512/m16bcst, and store the result in zmm1.
EVEX.128.66.MAP6.W0 B8 /rVFMADD231PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidMultiply packed FP16 values from xmm2 and AND AVX512VL) xmm3/m128/m16bcst, add to xmm1, and store OR AVX10.1 the result in xmm1.
EVEX.256.66.MAP6.W0 B8 /rVFMADD231PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidMultiply packed FP16 values from ymm2 and AND AVX512VL) ymm3/m256/m16bcst, add to ymm1, and store OR AVX10.1 the result in ymm1.
EVEX.512.66.MAP6.W0 B8 /rVFMADD231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidMultiply packed FP16 values from zmm2 and OR AVX10.1 zmm3/m512/m16bcst, add to zmm1, and store the result in zmm1.
EVEX.128.66.MAP6.W0 9C /rVFNMADD132PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidMultiply packed FP16 values from xmm1 and AND AVX512VL) xmm3/m128/m16bcst, and negate the value. OR AVX10.1 Add this value to xmm2, and store the result in xmm1.
EVEX.256.66.MAP6.W0 9C /rVFNMADD132PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidMultiply packed FP16 values from ymm1 and AND AVX512VL) ymm3/m256/m16bcst, and negate the value. OR AVX10.1 Add this value to ymm2, and store the result in ymm1.
EVEX.512.66.MAP6.W0 9C /rVFNMADD132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidMultiply packed FP16 values from zmm1 and OR AVX10.1 zmm3/m512/m16bcst, and negate the value. Add this value to zmm2, and store the result in zmm1.
EVEX.128.66.MAP6.W0 AC /rVFNMADD213PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidMultiply packed FP16 values from xmm1 and AND AVX512VL) xmm2, and negate the value. Add this value to OR AVX10.1 xmm3/m128/m16bcst, and store the result in xmm1.
EVEX.256.66.MAP6.W0 AC /rVFNMADD213PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcst Opcode/ InstructionAValidValidMultiply packed FP16 values from ymm1 and AND AVX512VL) ymm2, and negate the value. Add this value to OR AVX10.1 ymm3/m256/m16bcst, and store the result in ymm1. Op/ 64 /32 CPUID Feature Description En Bi Su t Mode Flag pport
EVEX.512.66.MAP6.W0 AC /rVFNMADD213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}a vMultiply packed FP16 values from zmm1 and OR AVX10.1 zmm2, and negate the value. Add this value to zmm3/m512/m16bcst, and store the result in zmm1.
EVEX.128.66.MAP6.W0 BC /rVFNMADD231PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcsta vMultiply packed FP16 values from xmm2 and AND AVX512VL) xmm3/m128/m16bcst, and negate the value. OR AVX10.1 Add this value to xmm1, and store the result in xmm1.
EVEX.256.66.MAP6.W0 BC /rVFNMADD231PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcsta vMultiply packed FP16 values from ymm2 and AND AVX512VL) ymm3/m256/m16bcst, and negate the value. OR AVX10.1 Add this value to ymm1, and store the result in ymm1.
EVEX.512.66.MAP6.W0 BC /rVFNMADD231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}a vMultiply packed FP16 values from zmm2 and OR AVX10.1 zmm3/m512/m16bcst, and negate the value. Add this value to zmm1, and store the result in zmm1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

This instruction performs a packed multiply-add or negated multiply-add computation on FP16 values using three source operands and writes the results in the destination operand. The destination operand is also the first source operand. The "N" (negated) forms of this instruction add the negated infinite precision intermediate product to the corresponding remaining operand. The notation' "132", "213" and "231" indicate the use of the operands in +/-A * B + C, where each digit corresponds to the operand number, with the destination being operand 1; see Table 5-5.

The destination elements are updated according to the writemask.

       Notation  Table 5-5. VF[,N]MADD[132,213,231]PH Notation for Operands
          132                                                                       Operands

231

          213                                                             dest = +/- dest*src3+src2

dest = +/- src2src3+dest dest = +/- src2dest+src3

Operation

VF[,N]MADD132PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
VL = 128, 256 or 512
KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):
    SET_RM(EVEX.RC)

ELSE
    SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF *negative form*:
                DEST.fp16[j] := RoundFPControl(-DEST.fp16[j]*SRC3.fp16[j] + SRC2.fp16[j])
          ELSE:
                DEST.fp16[j] := RoundFPControl(DEST.fp16[j]*SRC3.fp16[j] + SRC2.fp16[j])
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VF[,N]MADD132PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a memory source
VL = 128, 256 or 512
KL := VL/16

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF EVEX.b = 1:
                t3 := SRC3.fp16[0]
          ELSE:
                t3 := SRC3.fp16[j]
          IF *negative form*:
                DEST.fp16[j] := RoundFPControl(-DEST.fp16[j] * t3 + SRC2.fp16[j])
          ELSE:
                DEST.fp16[j] := RoundFPControl(DEST.fp16[j] * t3 + SRC2.fp16[j])
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0


VF[,N]MADD213PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
VL = 128, 256 or 512
KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):
    SET_RM(EVEX.RC)

ELSE
    SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF *negative form*:
                DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j]*DEST.fp16[j] + SRC3.fp16[j])
          ELSE
                DEST.fp16[j] := RoundFPControl(SRC2.fp16[j]*DEST.fp16[j] + SRC3.fp16[j])
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VF[,N]MADD213PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a memory source
VL = 128, 256 or 512
KL := VL/16

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF EVEX.b = 1:
                t3 := SRC3.fp16[0]
          ELSE:
                t3 := SRC3.fp16[j]
          IF *negative form*:
                DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j] * DEST.fp16[j] + t3 )
          ELSE:
                DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * DEST.fp16[j] + t3 )
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0


VF[,N]MADD231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
VL = 128, 256 or 512
KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):
    SET_RM(EVEX.RC)

ELSE
    SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF *negative form:
                DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j]*SRC3.fp16[j] + DEST.fp16[j])
          ELSE:
                DEST.fp16[j] := RoundFPControl(SRC2.fp16[j]*SRC3.fp16[j] + DEST.fp16[j])
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VF[,N]MADD231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a memory source
VL = 128, 256 or 512
KL := VL/16

FOR j := 0 TO KL-1:
    IF k1[j] OR *no writemask*:
          IF EVEX.b = 1:
                t3 := SRC3.fp16[0]
          ELSE:
                t3 := SRC3.fp16[j]
          IF *negative form*:
                DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j] * t3 + DEST.fp16[j] )
          ELSE:
                DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * t3 + DEST.fp16[j] )
    ELSE IF *zeroing*:
          DEST.fp16[j] := 0
    // else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VFMADD132PH, VFMADD213PH , and VFMADD231PH: __m128h _mm_fmadd_ph (__m128h a, __m128h b, __m128h c);
__m128h _mm_mask_fmadd_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);
__m128h _mm_mask3_fmadd_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fmadd_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);
__m256h _mm256_fmadd_ph (__m256h a, __m256h b, __m256h c);
__m256h _mm256_mask_fmadd_ph (__m256h a, __mmask16 k, __m256h b, __m256h c);
__m256h _mm256_mask3_fmadd_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fmadd_ph (__mmask16 k, __m256h a, __m256h b, __m256h c);
__m512h _mm512_fmadd_ph (__m512h a, __m512h b, __m512h c);
__m512h _mm512_mask_fmadd_ph (__m512h a, __mmask32 k, __m512h b, __m512h c);
__m512h _mm512_mask3_fmadd_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fmadd_ph (__mmask32 k, __m512h a, __m512h b, __m512h c);
__m512h _mm512_fmadd_round_ph (__m512h a, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fmadd_round_ph (__m512h a, __mmask32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fmadd_round_ph (__m512h a, __m512h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fmadd_round_ph (__mmask32 k, __m512h a, __m512h b, __m512h c, const int rounding);
VFNMADD132PH, VFNMADD213PH, and VFNMADD231PH: __m128h _mm_fnmadd_ph (__m128h a, __m128h b, __m128h c);
__m128h _mm_mask_fnmadd_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);
__m128h _mm_mask3_fnmadd_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fnmadd_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);
__m256h _mm256_fnmadd_ph (__m256h a, __m256h b, __m256h c);
__m256h _mm256_mask_fnmadd_ph (__m256h a, __mmask16 k, __m256h b, __m256h c);
__m256h _mm256_mask3_fnmadd_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fnmadd_ph (__mmask16 k, __m256h a, __m256h b, __m256h c);
__m512h _mm512_fnmadd_ph (__m512h a, __m512h b, __m512h c);
__m512h _mm512_mask_fnmadd_ph (__m512h a, __mmask32 k, __m512h b, __m512h c);
__m512h _mm512_mask3_fnmadd_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fnmadd_ph (__mmask32 k, __m512h a, __m512h b, __m512h c);
__m512h _mm512_fnmadd_round_ph (__m512h a, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fnmadd_round_ph (__m512h a, __mmask32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fnmadd_round_ph (__m512h a, __m512h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fnmadd_round_ph (__mmask32 k, __m512h a, __m512h b, __m512h c, const int rounding);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-48, "Type E2 Class Exception Conditions."

Sources