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Source code

VPEXPANDB, VPEXPANDW

Expand Byte/Word Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W0 62 /rVPEXPANDB xmm1{k1}{z}, m128AValidValidExpands up to 128 bits of packed byte values AND AVX512VL) OR AVX10.1 from m128 to xmm1 with writemask k1.
EVEX.128.66.0F38.W0 62 /rVPEXPANDB xmm1{k1}{z}, xmm2BValidValidExpands up to 128 bits of packed byte values AND AVX512VL) OR AVX10.1 from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W0 62 /rVPEXPANDB ymm1{k1}{z}, m256AValidValidExpands up to 256 bits of packed byte values AND AVX512VL) OR AVX10.1 from m256 to ymm1 with writemask k1.
EVEX.256.66.0F38.W0 62 /rVPEXPANDB ymm1{k1}{z}, ymm2BValidValidExpands up to 256 bits of packed byte values AND AVX512VL) OR AVX10.1 from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W0 62 /rVPEXPANDB zmm1{k1}{z}, m512AValidValidExpands up to 512 bits of packed byte values OR AVX10.1 from m512 to zmm1 with writemask k1.
EVEX.512.66.0F38.W0 62 /rVPEXPANDB zmm1{k1}{z}, zmm2BValidValidExpands up to 512 bits of packed byte values OR AVX10.1 from zmm2 to zmm1 with writemask k1.
EVEX.128.66.0F38.W1 62 /rVPEXPANDW xmm1{k1}{z}, m128AValidValidExpands up to 128 bits of packed word values AND AVX512VL) OR AVX10.1 from m128 to xmm1 with writemask k1.
EVEX.128.66.0F38.W1 62 /rVPEXPANDW xmm1{k1}{z}, xmm2BValidValidExpands up to 128 bits of packed word values AND AVX512VL) OR AVX10.1 from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W1 62 /rVPEXPANDW ymm1{k1}{z}, m256AValidValidExpands up to 256 bits of packed word values AND AVX512VL) OR AVX10.1 from m256 to ymm1 with writemask k1.
EVEX.256.66.0F38.W1 62 /rVPEXPANDW ymm1{k1}{z}, ymm2BValidValidExpands up to 256 bits of packed word values AND AVX512VL) OR AVX10.1 from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W1 62 /rVPEXPANDW zmm1{k1}{z}, m512AValidValidExpands up to 512 bits of packed word values OR AVX10.1 from m512 to zmm1 with writemask k1.
EVEX.512.66.0F38.W1 62 /rVPEXPANDW zmm1{k1}{z}, zmm2BValidValidExpands up to 512 bits of packed byte integer OR AVX10.1 values from zmm2 to zmm1 with writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Tuple1 Scalar

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Expands (loads) up to 64 byte integer values or 32 word integer values from the source operand (memory operand) to the destination operand (register operand), based on the active elements determined by the writemask operand.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Moves 128, 256 or 512 bits of packed byte integer values from the source operand (memory operand) to the destination operand (register operand). This instruction is used to load from an int8 vector register or memory location

while inserting the data into sparse elements of destination vector register using the active elements pointed out by the operand writemask.

This instruction supports memory fault suppression.

Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

Operation

VPEXPANDB

(KL, VL) = (16, 128), (32, 256), (64, 512)

k := 0

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

        DEST.byte[j] := SRC.byte[k];

        k := k + 1

        ELSE:

           IF *merging-masking*:

                    *DEST.byte[j] remains unchanged*

                    ELSE:                   ; zeroing-masking

                     DEST.byte[j] := 0

DEST[MAX_VL-1:VL] := 0

VPEXPANDW

(KL, VL) = (8,128), (16,256), (32, 512)

k := 0

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

        DEST.word[j] := SRC.word[k];

        k := k + 1

        ELSE:

           IF *merging-masking*:

                    *DEST.word[j] remains unchanged*

                    ELSE:                   ; zeroing-masking

                     DEST.word[j] := 0

DEST[MAX_VL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPEXPAND __m128i _mm_mask_expand_epi8(__m128i, __mmask16, __m128i);
VPEXPAND __m128i _mm_maskz_expand_epi8(__mmask16, __m128i);
VPEXPAND __m128i _mm_mask_expandloadu_epi8(__m128i, __mmask16, const void*);
VPEXPAND __m128i _mm_maskz_expandloadu_epi8(__mmask16, const void*);
VPEXPAND __m256i _mm256_mask_expand_epi8(__m256i, __mmask32, __m256i);
VPEXPAND __m256i _mm256_maskz_expand_epi8(__mmask32, __m256i);
VPEXPAND __m256i _mm256_mask_expandloadu_epi8(__m256i, __mmask32, const void*);
VPEXPAND __m256i _mm256_maskz_expandloadu_epi8(__mmask32, const void*);
VPEXPAND __m512i _mm512_mask_expand_epi8(__m512i, __mmask64, __m512i);
VPEXPAND __m512i _mm512_maskz_expand_epi8(__mmask64, __m512i);
VPEXPAND __m512i _mm512_mask_expandloadu_epi8(__m512i, __mmask64, const void*);
VPEXPAND __m512i _mm512_maskz_expandloadu_epi8(__mmask64, const void*);
VPEXPANDW __m128i _mm_mask_expand_epi16(__m128i, __mmask8, __m128i);
VPEXPANDW __m128i _mm_maskz_expand_epi16(__mmask8, __m128i);
VPEXPANDW __m128i _mm_mask_expandloadu_epi16(__m128i, __mmask8, const void*);
VPEXPANDW __m128i _mm_maskz_expandloadu_epi16(__mmask8, const void *);
VPEXPANDW __m256i _mm256_mask_expand_epi16(__m256i, __mmask16, __m256i);
VPEXPANDW __m256i _mm256_maskz_expand_epi16(__mmask16, __m256i);
VPEXPANDW __m256i _mm256_mask_expandloadu_epi16(__m256i, __mmask16, const void*);
VPEXPANDW __m256i _mm256_maskz_expandloadu_epi16(__mmask16, const void*);
VPEXPANDW __m512i _mm512_mask_expand_epi16(__m512i, __mmask32, __m512i);
VPEXPANDW __m512i _mm512_maskz_expand_epi16(__mmask32, __m512i);
VPEXPANDW __m512i _mm512_mask_expandloadu_epi16(__m512i, __mmask32, const void*);
VPEXPANDW __m512i _mm512_maskz_expandloadu_epi16(__mmask32, const void*);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, "Type E4 Class Exception Conditions."

Sources