PMINSB, PMINSW

Minimum of Packed Signed Integers

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`NP 0F EA /r1`	`PMINSW mm1, mm2/m64`	A	Valid	Valid	Compare signed word integers in mm2/m64 and mm1 and return minimum values.
`66 0F 38 38 /r`	`PMINSB xmm1, xmm2/m128`	A	Valid	Valid	Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1.
`66 0F EA /r`	`PMINSW xmm1, xmm2/m128`	A	Valid	Valid	Compare packed signed word integers in xmm2/m128 and xmm1 and store packed minimum values in xmm1.
`VEX.128.66.0F38 38 /r`	`VPMINSB xmm1, xmm2, xmm3/m128`	B	Valid	Valid	Compare packed signed byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1.
`VEX.128.66.0F EA /r`	`VPMINSW xmm1, xmm2, xmm3/m128`	B	Valid	Valid	Compare packed signed word integers in xmm3/m128 and xmm2 and return packed minimum values in xmm1.
`VEX.256.66.0F38 38 /r`	`VPMINSB ymm1, ymm2, ymm3/m256`	B	Valid	Valid	Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1.
`VEX.256.66.0F EA /r`	`VPMINSW ymm1, ymm2, ymm3/m256`	B	Valid	Valid	Compare packed signed word integers in ymm3/m256 and ymm2 and return packed minimum values in ymm1.
`EVEX.128.66.0F38.WIG 38 /r`	`VPMINSB xmm1{k1}{z}, xmm2, xmm3/m128`	C	Valid	Valid	Compare packed signed byte integers in xmm2 and AVX512BW) OR xmm3/m128 and store packed minimum values in AVX10.1 xmm1 under writemask k1.
`EVEX.256.66.0F38.WIG 38 /r`	`VPMINSB ymm1{k1}{z}, ymm2, ymm3/m256`	C	Valid	Valid	Compare packed signed byte integers in ymm2 and AVX512BW) OR ymm3/m256 and store packed minimum values in AVX10.1 ymm1 under writemask k1.
`EVEX.512.66.0F38.WIG 38 /r`	`VPMINSB zmm1{k1}{z}, zmm2, zmm3/m512`	C	Valid	Valid	Compare packed signed byte integers in zmm2 and AVX10.1 zmm3/m512 and store packed minimum values in zmm1 under writemask k1.
`EVEX.128.66.0F.WIG EA /r`	`VPMINSW xmm1{k1}{z}, xmm2, xmm3/m128`	C	Valid	Valid	Compare packed signed word integers in xmm2 AVX512BW) OR and xmm3/m128 and store packed minimum AVX10.1 values in xmm1 under writemask k1.
`EVEX.256.66.0F.WIG EA /r`	`VPMINSW ymm1{k1}{z}, ymm2, ymm3/m256`	C	Valid	Valid	Compare packed signed word integers in ymm2 AVX512BW) OR and ymm3/m256 and store packed minimum AVX10.1 values in ymm1 under writemask k1.
`EVEX.512.66.0F.WIG EA /r`	`VPMINSW zmm1{k1}{z}, zmm2, zmm3/m512`	C	Valid	Valid	Compare packed signed word integers in zmm2 and AVX10.1 zmm3/m512 and store packed minimum values in zmm1 under writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

B

modrm.reg escrituraModRM byte, reg field (bits 5-3)
vex.vvvv lecturaVEX prefix, vvvv field (inverted)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

C

modrm.reg escrituraModRM byte, reg field (bits 5-3)
evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full Mem

Measured cost

Loading measurements from arch-data...

Description

Performs a SIMD compare of the packed signed byte, word, or dword integers in the second source operand and the first source operand and returns the minimum value for each pair of integers to the destination operand.

Legacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.

VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1.

Operation

PMINSW (64-bit Operands)
    IF DEST[15:0] < SRC[15:0] THEN
          DEST[15:0] := DEST[15:0];
    ELSE
          DEST[15:0] := SRC[15:0]; FI;
    (* Repeat operation for 2nd and 3rd words in source and destination operands *)
    IF DEST[63:48] < SRC[63:48] THEN
          DEST[63:48] := DEST[63:48];
    ELSE
          DEST[63:48] := SRC[63:48]; FI;

PMINSB (128-bit Legacy SSE Version)
    IF DEST[7:0] < SRC[7:0] THEN
          DEST[7:0] := DEST[7:0];
    ELSE
          DEST[15:0] := SRC[7:0]; FI;
    (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
    IF DEST[127:120] < SRC[127:120] THEN
          DEST[127:120] := DEST[127:120];
    ELSE
          DEST[127:120] := SRC[127:120]; FI;

DEST[MAXVL-1:128] (Unmodified)


VPMINSB (VEX.128 Encoded Version)
    IF SRC1[7:0] < SRC2[7:0] THEN
          DEST[7:0] := SRC1[7:0];
    ELSE
          DEST[7:0] := SRC2[7:0]; FI;
    (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
    IF SRC1[127:120] < SRC2[127:120] THEN
          DEST[127:120] := SRC1[127:120];
    ELSE
          DEST[127:120] := SRC2[127:120]; FI;

DEST[MAXVL-1:128] := 0

VPMINSB (VEX.256 Encoded Version)
    IF SRC1[7:0] < SRC2[7:0] THEN
          DEST[7:0] := SRC1[7:0];
    ELSE
          DEST[15:0] := SRC2[7:0]; FI;
    (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
    IF SRC1[255:248] < SRC2[255:248] THEN
          DEST[255:248] := SRC1[255:248];
    ELSE
          DEST[255:248] := SRC2[255:248]; FI;

DEST[MAXVL-1:256] := 0

VPMINSB (EVEX Encoded Versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask* THEN

     IF SRC1[i+7:i] < SRC2[i+7:i]

            THEN DEST[i+7:i] := SRC1[i+7:i];

            ELSE DEST[i+7:i] := SRC2[i+7:i];

     FI;

     ELSE

            IF *merging-masking*                  ; merging-masking

                THEN *DEST[i+7:i] remains unchanged*

                ELSE                              ; zeroing-masking

                    DEST[i+7:i] := 0

            FI

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PMINSW (128-bit Legacy SSE Version)
    IF DEST[15:0] < SRC[15:0] THEN
          DEST[15:0] := DEST[15:0];
    ELSE
          DEST[15:0] := SRC[15:0]; FI;
    (* Repeat operation for 2nd through 7th words in source and destination operands *)
    IF DEST[127:112] < SRC[127:112] THEN
          DEST[127:112] := DEST[127:112];
    ELSE
          DEST[127:112] := SRC[127:112]; FI;

DEST[MAXVL-1:128] (Unmodified)


VPMINSW (VEX.128 Encoded Version)
    IF SRC1[15:0] < SRC2[15:0] THEN
          DEST[15:0] := SRC1[15:0];
    ELSE
          DEST[15:0] := SRC2[15:0]; FI;
    (* Repeat operation for 2nd through 7th words in source and destination operands *)
    IF SRC1[127:112] < SRC2[127:112] THEN
          DEST[127:112] := SRC1[127:112];
    ELSE
          DEST[127:112] := SRC2[127:112]; FI;

DEST[MAXVL-1:128] := 0

VPMINSW (VEX.256 Encoded Version)
    IF SRC1[15:0] < SRC2[15:0] THEN
          DEST[15:0] := SRC1[15:0];
    ELSE
          DEST[15:0] := SRC2[15:0]; FI;
    (* Repeat operation for 2nd through 15th words in source and destination operands *)
    IF SRC1[255:240] < SRC2[255:240] THEN
          DEST[255:240] := SRC1[255:240];
    ELSE
          DEST[255:240] := SRC2[255:240]; FI;

DEST[MAXVL-1:256] := 0

VPMINSW (EVEX Encoded Versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask* THEN

     IF SRC1[i+15:i] < SRC2[i+15:i]

             THEN DEST[i+15:i] := SRC1[i+15:i];

             ELSE DEST[i+15:i] := SRC2[i+15:i];

     FI;

     ELSE

             IF *merging-masking*                 ; merging-masking

                 THEN *DEST[i+15:i] remains unchanged*

                 ELSE                             ; zeroing-masking

                    DEST[i+15:i] := 0

             FI

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);
VPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);
VPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);
VPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);
VPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_mask_min_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);
(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);
(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b) VPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);
VPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b) PMINSW__m64 _mm_min_pi16 (__m64 a, __m64 b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, "Type 4 Class Exception Conditions."

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, "Type E4 Class Exception Conditions."

Additionally:

#MF               (64-bit operations only) If there is a pending x87 FPU exception.

PMINSB, PMINSW

Encodings

Operand encoding

A

B

C

Measured cost

Description#

Operation#

Intel C/C++ compiler intrinsics#

SIMD Floating-Point Exceptions#

Other Exceptions#

Sources

Description

Operation

Intel C/C++ compiler intrinsics

SIMD Floating-Point Exceptions

Other Exceptions