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VPCOMPRESSQ

Store Sparse Packed Quadword Integer Values Into Dense Memory/Register

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W1 8B /rVPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2AValidValidCompress packed quadword integer values AVX512F) OR AVX10.1 from xmm2 to xmm1/m128 using control mask k1.
EVEX.256.66.0F38.W1 8B /rVPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2AValidValidCompress packed quadword integer values AVX512F) OR AVX10.1 from ymm2 to ymm1/m256 using control mask k1.
EVEX.512.66.0F38.W1 8B /rVPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2AValidValidCompress packed quadword integer values OR AVX10.1 from zmm2 to zmm1/m512 using control mask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. modrm.reg lecturaModRM byte, reg field (bits 5-3)

Tupla: Tuple1 Scalar

Measured cost

Loading measurements from arch-data...

Description

Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destination operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the destination starting from the low element of the destination operand.

Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z must be zero.

Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper bits are zeroed.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

Operation

VPCOMPRESSQ (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1

    i := j * 64
    IF k1[j] OR *no controlmask*

          THEN
                DEST[k+SIZE-1:k] := SRC[i+63:i]
                k := k + SIZE

    FI;

ENFOR

VPCOMPRESSQ (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1

    i := j * 64
    IF k1[j] OR *no controlmask*

          THEN
                DEST[k+SIZE-1:k] := SRC[i+63:i]
                k := k + SIZE

    FI;
ENDFOR
IF *merging-masking*

            THEN *DEST[VL-1:k] remains unchanged*
            ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);
VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, "Type E4 Class Exception Conditions."

Sources