VPMOVDW, VPMOVSDW, VPMOVUSDW

Down Convert DWord to Word

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`EVEX.128.F3.0F38.W0 33 /r`	`VPMOVDW xmm1/m64 {k1}{z}, xmm2`	A	Valid	Valid	Converts 4 packed double-word integers AVX512F) OR AVX10.1 from xmm2 into 4 packed word integers in xmm1/m64 with truncation under writemask k1.
`EVEX.128.F3.0F38.W0 23 /r`	`VPMOVSDW xmm1/m64 {k1}{z}, xmm2`	A	Valid	Valid	Converts 4 packed signed double-word AVX512F) OR AVX10.1 integers from xmm2 into 4 packed signed word integers in ymm1/m64 using signed saturation under writemask k1.
`EVEX.128.F3.0F38.W0 13 /r`	`VPMOVUSDW xmm1/m64 {k1}{z}, xmm2`	A	Valid	Valid	Converts 4 packed unsigned double-word AVX512F) OR AVX10.1 integers from xmm2 into 4 packed unsigned word integers in xmm1/m64 using unsigned saturation under writemask k1.
`EVEX.256.F3.0F38.W0 33 /r`	`VPMOVDW xmm1/m128 {k1}{z}, ymm2`	A	Valid	Valid	Converts 8 packed double-word integers AVX512F) OR AVX10.1 from ymm2 into 8 packed word integers in xmm1/m128 with truncation under writemask k1.
`EVEX.256.F3.0F38.W0 23 /r`	`VPMOVSDW xmm1/m128 {k1}{z}, ymm2`	A	Valid	Valid	Converts 8 packed signed double-word AVX512F) OR AVX10.1 integers from ymm2 into 8 packed signed word integers in xmm1/m128 using signed saturation under writemask k1.
`EVEX.256.F3.0F38.W0 13 /r`	`VPMOVUSDW xmm1/m128 {k1}{z}, ymm2`	A	Valid	Valid	Converts 8 packed unsigned double-word AVX512F) OR integers from ymm2 into 8 packed unsigned AVX10.1 word integers in xmm1/m128 using unsigned saturation under writemask k1.
`EVEX.512.F3.0F38.W0 33 /r`	`VPMOVDW ymm1/m256 {k1}{z}, zmm2`	A	Valid	Valid	Converts 16 packed double-word integers OR AVX10.1 from zmm2 into 16 packed word integers in ymm1/m256 with truncation under writemask k1.
`EVEX.512.F3.0F38.W0 23 /r`	`VPMOVSDW ymm1/m256 {k1}{z}, zmm2`	A	Valid	Valid	Converts 16 packed signed double-word OR AVX10.1 integers from zmm2 into 16 packed signed word integers in ymm1/m256 using signed saturation under writemask k1.
`EVEX.512.F3.0F38.W0 13 /r`	`VPMOVUSDW ymm1/m256 {k1}{z}, zmm2`	A	Valid	Valid	Converts 16 packed unsigned double-word OR AVX10.1 integers from zmm2 into 16 packed unsigned word integers in ymm1/m256 using unsigned saturation under writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
modrm.reg lecturaModRM byte, reg field (bits 5-3)

Tupla: Half Mem

Measured cost

Loading measurements from arch-data...

Description

VPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words using truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation. VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.

The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a 256/128/64-bit memory location.

Down-converted word elements are written to the destination operand (the first operand) from the least-significant word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL- 1:256/128/64) of the register destination are zeroed.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VPMOVDW instruction (EVEX encoded versions) when dest is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 16

m := j * 32

IF k1[j] OR *no writemask*

           THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])

           ELSE

             IF *merging-masking*           ; merging-masking

                    THEN *DEST[i+15:i] remains unchanged*

                    ELSE *zeroing-masking*  ; zeroing-masking

                    DEST[i+15:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0;

VPMOVDW instruction (EVEX encoded versions) when dest is memory
    (KL, VL) = (4, 128), (8, 256), (16, 512)
    FOR j := 0 TO KL-1
          i := j * 16
          m := j * 32
          IF k1[j] OR *no writemask*
                THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])
                ELSE
                      *DEST[i+15:i] remains unchanged* ; merging-masking
          FI;
    ENDFOR

VPMOVSDW instruction (EVEX encoded versions) when dest is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 16

m := j * 32

IF k1[j] OR *no writemask*

           THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])

           ELSE

             IF *merging-masking*           ; merging-masking

                    THEN *DEST[i+15:i] remains unchanged*

                    ELSE *zeroing-masking*  ; zeroing-masking

                    DEST[i+15:i] := 0


                  FI
      FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;

VPMOVSDW instruction (EVEX encoded versions) when dest is memory
    (KL, VL) = (4, 128), (8, 256), (16, 512)
    FOR j := 0 TO KL-1
          i := j * 16
          m := j * 32
          IF k1[j] OR *no writemask*
                THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])
                ELSE
                      *DEST[i+15:i] remains unchanged* ; merging-masking
          FI;
    ENDFOR

VPMOVUSDW instruction (EVEX encoded versions) when dest is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 16

m := j * 32

IF k1[j] OR *no writemask*

        THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])

        ELSE

             IF *merging-masking*           ; merging-masking

                    THEN *DEST[i+15:i] remains unchanged*

                    ELSE *zeroing-masking*  ; zeroing-masking

                    DEST[i+15:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0;

VPMOVUSDW instruction (EVEX encoded versions) when dest is memory
    (KL, VL) = (4, 128), (8, 256), (16, 512)
    FOR j := 0 TO KL-1
          i := j * 16
          m := j * 32
          IF k1[j] OR *no writemask*
                THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
                ELSE
                      *DEST[i+15:i] remains unchanged* ; merging-masking
          FI;
    ENDFOR

Intel C/C++ compiler intrinsics

VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);
VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);
VPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);
VPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);
VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);
VPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);
VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);
VPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);
VPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);
VPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);
VPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);
VPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-55, "Type E6 Class Exception Conditions."

Additionally: If EVEX.vvvv != 1111B.

#UD

VPMOVDW, VPMOVSDW, VPMOVUSDW

Encodings

Operand encoding

A

Measured cost

Description#

Operation#

Intel C/C++ compiler intrinsics#

SIMD Floating-Point Exceptions#

Other Exceptions#

Sources

Description

Operation

Intel C/C++ compiler intrinsics

SIMD Floating-Point Exceptions

Other Exceptions