LGDT, LIDT

Load Global/Interrupt Descriptor Table Register

stableVMJITAOTinstruction

Encodings

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

Measured cost

Description#

Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is filled with zeros.

The LGDT and LIDT instructions are used only in operating-system software; they are not used in application programs. They are the only instructions that directly load a linear address (that is, not a segment-relative address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode.

In 64-bit mode, the instruction's operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the summary chart at the beginning of this section for encoding data and limits.

See "SGDT--Store Global Descriptor Table Register" in Chapter 4, of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR.

Operation#

IF Instruction is LIDT
    THEN

        IF OperandSize = 16

                THEN
                      IDTR(Limit) := SRC[0:15];
                      IDTR(Base) := SRC[16:47] AND 00FFFFFFH;

                ELSE IF 32-bit Operand Size
                      THEN
                            IDTR(Limit) := SRC[0:15];
                            IDTR(Base) := SRC[16:47];
                      FI;

                ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
                      THEN
                            IDTR(Limit) := SRC[0:15];
                            IDTR(Base) := SRC[16:79];
                      FI;

          FI;
    ELSE (* Instruction is LGDT *)

        IF OperandSize = 16

                THEN
                      GDTR(Limit) := SRC[0:15];
                      GDTR(Base) := SRC[16:47] AND 00FFFFFFH;

                ELSE IF 32-bit Operand Size
                      THEN
                            GDTR(Limit) := SRC[0:15];
                            GDTR(Base) := SRC[16:47];
                      FI;

                ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
                      THEN
                            GDTR(Limit) := SRC[0:15];
                            GDTR(Base) := SRC[16:79];
                      FI;

          FI;
FI;

Flags affected#

None.

Exceptions

Sources

• This instruction in the Intel manual
• Latency and throughput per microarchitecture