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Source code

VPBROADCASTM

Broadcast Mask to Vector Register

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.F3.0F38.W1 2A /rVPBROADCASTMB2Q xmm1, k1RMValidValidBroadcast low byte value in k1 to two locations in AVX512CD) OR AVX10.1 xmm1.
EVEX.256.F3.0F38.W1 2A /rVPBROADCASTMB2Q ymm1, k1RMValidValidBroadcast low byte value in k1 to four locations in AVX512CD) OR AVX10.1 ymm1.
EVEX.512.F3.0F38.W1 2A /rVPBROADCASTMB2Q zmm1, k1RMValidValidBroadcast low byte value in k1 to eight locations in OR AVX10.1 zmm1.
EVEX.128.F3.0F38.W0 3A /rVPBROADCASTMW2D xmm1, k1RMValidValidBroadcast low word value in k1 to four locations in AVX512CD) OR AVX10.1 xmm1.
EVEX.256.F3.0F38.W0 3A /rVPBROADCASTMW2D ymm1, k1RMValidValidBroadcast low word value in k1 to eight locations AVX512CD) OR AVX10.1 in ymm1.
EVEX.512.F3.0F38.W0 3A /rVPBROADCASTMW2D zmm1, k1RMValidValidBroadcast low word value in k1 to sixteen OR AVX10.1 locations in zmm1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Not measured: it does not run on 64-bit processors.

Description

Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register. The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VPBROADCASTMB2Q
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1

    i := j*64
    DEST[i+63:i] := ZeroExtend(SRC[7:0])
ENDFOR
DEST[MAXVL-1:VL] := 0


VPBROADCASTMW2D
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1

    i := j*32
    DEST[i+31:i] := ZeroExtend(SRC[15:0])
ENDFOR
DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);
VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);

SIMD Floating-Point Exceptions

None

Other Exceptions

EVEX-encoded instruction, see Table 2-56, "Type E6NF Class Exception Conditions."

Sources