KANDW, KANDB, KANDQ, KANDD
Bitwise Logical AND Masks
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
VEX.L1.0F.W0 41 /r | KANDW k1, k2, k3 | RVR | Valid | Valid | Bitwise AND 16 bits masks k2 and k3 and place result in k1. OR AVX10.1 |
VEX.L1.66.0F.W0 41 /r | KANDB k1, k2, k3 | RVR | Valid | Valid | Bitwise AND 8 bits masks k2 and k3 and place result in k1. OR AVX10.1 |
VEX.L1.0F.W1 41 /r | KANDQ k1, k2, k3 | RVR | Valid | Valid | Bitwise AND 64 bits masks k2 and k3 and place result in k1. OR AVX10.1 |
VEX.L1.66.0F.W1 41 /r | KANDD k1, k2, k3 | RVR | Valid | Valid | Bitwise AND 32 bits masks k2 and k3 and place result in k1. OR AVX10.1 |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RVR
modrm.regescrituraModRM byte, reg field (bits 5-3)vex.vvvvlecturaVEX prefix, vvvv field (inverted)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
Measured cost
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Description
Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.
Operation
KANDW
DEST[15:0] := SRC1[15:0] BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] := 0
KANDB
DEST[7:0] := SRC1[7:0] BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] := 0
KANDQ
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] := 0
KANDD
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] := 0Intel C/C++ compiler intrinsics
KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);Flags affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-65, "TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)."