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Source code

XCHG

Exchange Register/Memory With Register

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
90+rwXCHG AX, r16OValidValidExchange r16 with AX.
90+rwXCHG r16, AXOValidValidExchange AX with r16.
90+rdXCHG EAX, r32OValidValidExchange r32 with EAX.
REX.W + 90+rdXCHG RAX, r64OValidNot encodableExchange r64 with RAX.
90+rdXCHG r32, EAXOValidValidExchange EAX with r32.
REX.W + 90+rdXCHG r64, RAXOValidNot encodableExchange RAX with r64.
86 /rXCHG r/m8, r8MRValidValidExchange r8 (byte register) with byte from r/m8.
86 /rXCHG r8, r/m8RMValidValidExchange byte from r/m8 with r8 (byte register).
87 /rXCHG r/m16, r16MRValidValidExchange r16 with word from r/m16.
87 /rXCHG r16, r/m16RMValidValidExchange word from r/m16 with r16.
87 /rXCHG r/m32, r32MRValidValidExchange r32 with doubleword from r/m32.
REX.W + 87 /rXCHG r/m64, r64MRValidNot encodableExchange r64 with quadword from r/m64.
87 /rXCHG r32, r/m32RMValidValidExchange doubleword from r/m32 with r32.
REX.W + 87 /rXCHG r64, r/m64RMValidNot encodableExchange quadword from r/m64 with r64.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

O

  1. AX/EAX/RAX lectura y escritura
  2. opcode.reg lectura y escrituralow three bits of the opcode byte itself

O

  1. opcode.reg lectura y escrituralow three bits of the opcode byte itself
  2. AX/EAX/RAX lectura y escritura

MR

  1. modrm.rm lectura y escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. modrm.reg lecturaModRM byte, reg field (bits 5-3)

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Exchanges the contents of the destination (first) and source (second) operands. The operands can be two generalpurpose registers or a register and a memory location. If a memory operand is referenced, the processor's locking protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.)

This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See "Bus Locking" in Chapter 9 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information on bus locking.)

The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

NOTE

XCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size prefixes, including REX.W.

Operation

TEMP := DEST;
DEST := SRC;
SRC := TEMP;

Flags affected

None.

Exceptions

Protected mode
#GP(0)If either operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used but the destination is not a memory operand.
Real address mode
#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SSIf a memory operand effective address is outside the SS segment limit.
#UDIf the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 mode
#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made.
#UDIf the LOCK prefix is used but the destination is not a memory operand.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
#SS(0)If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf the LOCK prefix is used but the destination is not a memory operand.

Sources