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Source code

WRFSBASE, WRGSBASE

Write FS/GS Segment Base

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
F3 0F AE /2WRFSBASE r32MValidInvalidLoad the FS base address with the 32-bit value in the source register.
F3 REX.W 0F AE /2WRFSBASE r64MValidInvalidLoad the FS base address with the 64-bit value in the source register.
F3 0F AE /3WRGSBASE r32MValidInvalidLoad the GS base address with the 32-bit value in the source register.
F3 REX.W 0F AE /3WRGSBASE r64MValidInvalidLoad the GS base address with the 64-bit value in the source register.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

M

  1. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Loads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.

The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source register are ignored and upper 32 bits of the base address (for FS or GS) are cleared. This instruction is supported only in 64-bit mode.

Operation

FS/GS segment base address := SRC;

Flags affected

None.

C/C++ Compiler Intrinsic Equivalent

WRFSBASE void _writefsbase_u32( unsigned int ); WRFSBASE _writefsbase_u64( unsigned __int64 ); WRGSBASE void _writegsbase_u32( unsigned int ); WRGSBASE _writegsbase_u64( unsigned __int64 );

Exceptions

Protected mode
#UDThe WRFSBASE and WRGSBASE instructions are not recognized in protected mode.
Real address mode
#UDThe WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.
Virtual-8086 mode
#UDThe WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.
Compatibility mode
#UDThe WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.
64-bit mode
#UDIf the LOCK prefix is used. If CR4.FSGSBASE[bit 16] = 0. If CPUID.07H.00H:EBX.FSGSBASE[0] = 0
#GP(0)If the source register contains a non-canonical address.

Sources