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Source code

VPMOVB2M, VPMOVW2M, VPMOVD2M, VPMOVQ2M

Convert a Vector Register to a Mask

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.F3.0F38.W0 29 /rVPMOVB2M k1, xmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512BW) OR AVX10.1 most significant bit of the corresponding byte in XMM1.
EVEX.256.F3.0F38.W0 29 /rVPMOVB2M k1, ymm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512BW) OR AVX10.1 most significant bit of the corresponding byte in YMM1.
EVEX.512.F3.0F38.W0 29 /rVPMOVB2M k1, zmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the OR AVX10.1 most significant bit of the corresponding byte in ZMM1.
EVEX.128.F3.0F38.W1 29 /rVPMOVW2M k1, xmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512BW) OR AVX10.1 most significant bit of the corresponding word in XMM1.
EVEX.256.F3.0F38.W1 29 /rVPMOVW2M k1, ymm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512BW) OR AVX10.1 most significant bit of the corresponding word in YMM1.
EVEX.512.F3.0F38.W1 29 /rVPMOVW2M k1, zmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the OR AVX10.1 most significant bit of the corresponding word in ZMM1.
EVEX.128.F3.0F38.W0 39 /rVPMOVD2M k1, xmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512DQ) OR AVX10.1 most significant bit of the corresponding doubleword in XMM1.
EVEX.256.F3.0F38.W0 39 /rVPMOVD2M k1, ymm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512DQ) OR AVX10.1 most significant bit of the corresponding doubleword in YMM1.
EVEX.512.F3.0F38.W0 39 /rVPMOVD2M k1, zmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the OR AVX10.1 most significant bit of the corresponding doubleword in ZMM1.
EVEX.128.F3.0F38.W1 39 /rVPMOVQ2M k1, xmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512DQ) OR AVX10.1 most significant bit of the corresponding quadword in XMM1.
EVEX.256.F3.0F38.W1 39 /rVPMOVQ2M k1, ymm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the AVX512DQ) OR AVX10.1 most significant bit of the corresponding quadword in YMM1.
EVEX.512.F3.0F38.W1 39 /rVPMOVQ2M k1, zmm1RMValidValidSets each bit in k1 to 1 or 0 based on the value of the OR AVX10.1 most significant bit of the corresponding quadword in ZMM1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on the value of most significant bit of the corresponding element in the source register. The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1

    i := j * 8
    IF SRC[i+7]

          THEN DEST[j] := 1
          ELSE DEST[j] := 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1

    i := j * 16
    IF SRC[i+15]

          THEN DEST[j] := 1
          ELSE DEST[j] := 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1

    i := j * 32
    IF SRC[i+31]

          THEN DEST[j] := 1
          ELSE DEST[j] := 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1

    i := j * 64
    IF SRC[i+63]

          THEN DEST[j] := 1
          ELSE DEST[j] := 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

Intel C/C++ compiler intrinsics

VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-57, "Type E7NM Class Exception Conditions."

Additionally: If EVEX.vvvv != 1111B.

#UD

Sources