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Source code

PAND

Logical AND

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
NP 0F DB /r1PAND mm, mm/m64AValidValidBitwise AND mm/m64 and mm.
66 0F DB /rPAND xmm1, xmm2/m128AValidValidBitwise AND of xmm2/m128 and xmm1.
VEX.128.66.0F.WIG DB /rVPAND xmm1, xmm2, xmm3/m128BValidValidBitwise AND of xmm3/m128 and xmm.
VEX.256.66.0F.WIG DB /rVPAND ymm1, ymm2, ymm3/.m256BValidValidBitwise AND of ymm2, and ymm3/m256 and store result in ymm1.
EVEX.128.66.0F.W0 DB /rVPANDD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCValidValidBitwise AND of packed doubleword integers in AVX512F) OR xmm2 and xmm3/m128/m32bcst and store result AVX10.1 in xmm1 using writemask k1.
EVEX.256.66.0F.W0 DB /rVPANDD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCValidValidBitwise AND of packed doubleword integers in AVX512F) OR ymm2 and ymm3/m256/m32bcst and store result AVX10.1 in ymm1 using writemask k1.
EVEX.512.66.0F.W0 DB /rVPANDD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstCValidValidBitwise AND of packed doubleword integers in OR AVX10.1 zmm2 and zmm3/m512/m32bcst and store result in zmm1 using writemask k1.
EVEX.128.66.0F.W1 DB /rVPANDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCValidValidBitwise AND of packed quadword integers in xmm2 AVX512F) OR and xmm3/m128/m64bcst and store result in AVX10.1 xmm1 using writemask k1.
EVEX.256.66.0F.W1 DB /rVPANDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCValidValidBitwise AND of packed quadword integers in ymm2 AVX512F) OR and ymm3/m256/m64bcst and store result in AVX10.1 ymm1 using writemask k1.
EVEX.512.66.0F.W1 DB /rVPANDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCValidValidBitwise AND of packed quadword integers in zmm2 OR AVX10.1 and zmm3/m512/m64bcst and store result in zmm1 using writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

C

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

Performs a bitwise logical AND operation on the first source operand and second source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second operands are 1, otherwise it is set to 0.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 32/64-bit granularity.

VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.

Operation

PAND (64-bit Operand)
DEST := DEST AND SRC

PAND (128-bit Legacy SSE Version)
DEST := DEST AND SRC
DEST[MAXVL-1:128] (Unmodified)

VPAND (VEX.128 Encoded Version)
DEST := SRC1 AND SRC2
DEST[MAXVL-1:128] := 0

VPAND (VEX.256 Encoded Instruction)
DEST[255:0] := (SRC1[255:0] AND SRC2[255:0])
DEST[MAXVL-1:256] := 0

VPANDD (EVEX Encoded Versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

     THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                   THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[31:0]

                   ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[i+31:i]

             FI;

     ELSE

             IF *merging-masking*             ; merging-masking

                   THEN *DEST[i+31:i] remains unchanged*

                   ELSE                       ; zeroing-masking

                    DEST[i+31:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0


VPANDQ (EVEX Encoded Versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

     THEN

             IF (EVEX.b = 1) AND (SRC2 *is memory*)

                   THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[63:0]

                   ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[i+63:i]

             FI;

     ELSE

             IF *merging-masking*        ; merging-masking

                   THEN *DEST[i+63:i] remains unchanged*

                   ELSE                  ; zeroing-masking

                    DEST[i+63:i] := 0

             FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);
VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);
VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);
PAND __m64 _mm_and_si64 (__m64 m1, __m64 m2) (V)PAND __m128i _mm_and_si128 ( __m128i a, __m128i b) VPAND __m256i _mm256_and_si256 ( __m256i a, __m256i b);

Flags affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, "Type 4 Class Exception Conditions." EVEX-encoded instruction, see Table 2-51, "Type E4 Class Exception Conditions."

Sources