FICOM, FICOMP
Compare Integer
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
DE /2 | FICOM m16int | Valid | Valid | Compare ST(0) with m16int. | |
DA /2 | FICOM m32int | Valid | Valid | Compare ST(0) with m32int. | |
DE /3 | FICOMP m16int | Valid | Valid | Compare ST(0) with m16int and pop stack register. | |
DA /3 | FICOMP m32int | Valid | Valid | Compare ST(0) with m32int and pop stack register. |
Measured cost
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Description
Compares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). The integer value is converted to double extendedprecision floating-point format before the comparison is made.
FICOM/FICOMP Results
| Condition | C3 | C2 | C0 |
|---|---|---|---|
| > SRC | 0 | 0 | 0 |
| < SRC | 0 | 0 | 1 |
| = SRC | 1 | 0 | 0 |
| Unordered | 1 | 1 | 1 |
Operation
CASE (relation of operands) OF
ST(0) > SRC: C3, C2, C0 := 000;
ST(0) < SRC: C3, C2, C0 := 001;
ST(0) = SRC: C3, C2, C0 := 100;
Unordered: C3, C2, C0 := 111;
ESAC;
IF Instruction = FICOMP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1 Set to 0.
C0, C2, C3 See table on previous page.Floating-Point Exceptions
#IS Stack underflow occurred.#IA One or both operands are NaN values or have unsupported formats.#D One or both operands are denormal values.Exceptions
Protected mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |
Real address mode
#GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
#UD | If the LOCK prefix is used. |
Virtual-8086 mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
#UD | If the LOCK prefix is used. |
Compatibility mode
| Same exceptions as in protected mode. |
64-bit mode
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
#GP(0) | If the memory address is in a non-canonical form. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
#MF | If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |