FXSAVE

Save x87 FPU, MMX Technology, and SSE State

stableVMJITAOTinstruction

Encodings

Opcode	Instruction	Op/En	64-bit	Compat/Legacy	Description
`NP 0F AE /0`	`FXSAVE m512byte`	M	Valid	Valid	Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte.
`NP REX.W + 0F AE /0`	`FXSAVE64 m512byte`	M	Valid	Not encodable	Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

M

modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand. The content layout of the 512 byte region depends on whether the processor is operating in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode.

Bytes 464:511 are available to software use. The processor does not write to bytes 464:511 of an FXSAVE area.

The operation of FXSAVE in non-64-bit modes is described first.

Non-64-Bit Mode Operation

Table 3-45 shows the layout of the state information in memory when the processor is operating in legacy modes.

Non-64-Bit-Mode Layout of FXSAVE and FXRSTOR Memory Region

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Rsvd		FCS			FIP[31:0]			FOP	Rsvd	FTW		FSW			FCW 0

Non-64-Bit-Mode Layout of FXSAVE and FXRSTOR Memory Region (Contd.)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Rsvd		FCS			FIP[31:0]			FOP	Rsvd	FTW		FSW			FCW 0

Recreating FSAVE Format

Exponent	Exponent	Fraction	J and M	valid	bit
all 1's	all 0's	all 0's	bits		x87 FTW
0	0	0	0x	1	Special 10
0	0	0	1x	1	Valid 00
0	0	1	00	1	Special 10
0	0	1	10	1	Valid 00
0	1	0	0x	1	Special 10
0	1	0	1x	1	Special 10
0	1	1	00	1	Zero 01
0	1	1	10	1	Special 10
1	0	0	1x	1	Special 10
1	0	0	1x	1	Special 10
1	0	1	00	1	Special 10
1	0	1	10	1	Special 10

Layout of the 64-Bit Mode FXSAVE64 Map (Requires REX.W = 1)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FIP					FOP		Reserved FT	W	FSW		FCW	0

Layout of the 64-Bit Mode FXSAVE Map (REX.W = 0)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Rese	rved	FCS			FIP[31:	0]		FOP		Reserved	FTW	FSW		FCW	0
	MXCSR_	MASK			MXCSR			Reserved		FDS			FDP[31:0]		16

Operation

IF 64-Bit Mode
    THEN
          IF REX.W = 1
                THEN
                      DEST := Save64BitPromotedFxsave(x87 FPU, MMX, XMM15-XMM0,
                      MXCSR);
                ELSE
                      DEST := Save64BitDefaultFxsave(x87 FPU, MMX, XMM15-XMM0, MXCSR);
          FI;
    ELSE
          DEST := SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);

FI;

Exceptions

Protected mode

`#GP(0)`	For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See the description of the alignment check exception [#AC] below.)
`#SS(0)`	For an illegal address in the SS segment. #PF(fault-code) For a page fault.
`#NM`	If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1.
`#UD`	If CPUID.01H:EDX.FXSR[24] = 0.
`#UD`	If the LOCK prefix is used.
`#AC`	If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments).

Real address mode

`#GP`	If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
`#NM`	If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1.
`#UD`	If CPUID.01H:EDX.FXSR[24] = 0. If the LOCK prefix is used.

Virtual-8086 mode

	Same exceptions as in real address mode.
`#AC`	For unaligned memory reference.
`#UD`	If the LOCK prefix is used.

Compatibility mode

Same exceptions as in protected mode.

64-bit mode

`#SS(0)`	If a memory address referencing the SS segment is in a non-canonical form.
`#GP(0)`	If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault.
`#NM`	If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1.
`#UD`	If CPUID.01H:EDX.FXSR[24] = 0. If the LOCK prefix is used.
`#AC`	If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments). Implementation Note The order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both occur on an instruction boundary is given in Table 5-2 in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. This order vary for FXSAVE for different processor implementations.