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Source code

MOVQ2DQ

Move Quadword from MMX Technology to XMM Register

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
F3 0F D6 /rMOVQ2DQ xmm, mmRMValidValidMove quadword from mmx to low quadword of xmm.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

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Description

Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[63:0] := SRC[63:0];
DEST[127:64] := 00000000000000000H;

Intel C/C++ compiler intrinsics

MOVQ2DQ__128i _mm_movpi64_epi64 ( __m64 a);

SIMD Floating-Point Exceptions

None.

Exceptions

Protected mode
#NMIf CR0.TS[bit 3] = 1.
#UDIf CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[26] = 0. If the LOCK prefix is used.
#MFIf there is a pending x87 FPU exception.
Real address mode
Same exceptions as in protected mode.
Virtual-8086 mode
Same exceptions as in protected mode.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
Same exceptions as in protected mode.

Sources