ADDSUBPS

Packed Single Precision Floating-Point Add/Subtract

stableVMJITAOTinstruction

Encodings

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

Measured cost

Flags named

• CF Carry
• PF Parity
• AF Auxiliary carry
• ZF Zero
• SF Sign
• OF Overflow

Description#

Adds odd-numbered single precision floating-point values of the first source operand (second operand) with the corresponding single precision floating-point values from the second source operand (third operand); stores the result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered single precision floating-point values from the second source operand from the corresponding single precision floating values in the first source operand; stores the result into the even-numbered values of the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. See Figure 3-4.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.

ADDSUBPS xmm1, xmm2/m128

[127:96] [95:64] [63:32] [31:0] xmm2/ m128

xmm1[127:96] + xmm1[95:64] - xmm2/ xmm1[63:32] + xmm1[31:0] - RESULT:

xmm2/m128[127:96] m128[95:64] xmm2/m128[63:32] xmm2/m128[31:0] xmm1

[127:96] [95:64] [63:32] [31:0]

OM15992

Figure 3-4. ADDSUBPS--Packed Single Precision Floating-Point Add/Subtract

Operation#

ADDSUBPS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] - SRC[31:0]
DEST[63:32] := DEST[63:32] + SRC[63:32]
DEST[95:64] := DEST[95:64] - SRC[95:64]
DEST[127:96] := DEST[127:96] + SRC[127:96]
DEST[MAXVL-1:128] (Unmodified)

VADDSUBPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]
DEST[63:32] := SRC1[63:32] + SRC2[63:32]
DEST[95:64] := SRC1[95:64] - SRC2[95:64]
DEST[127:96] := SRC1[127:96] + SRC2[127:96]
DEST[MAXVL-1:128] := 0

VADDSUBPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]
DEST[63:32] := SRC1[63:32] + SRC2[63:32]
DEST[95:64] := SRC1[95:64] - SRC2[95:64]
DEST[127:96] := SRC1[127:96] + SRC2[127:96]
DEST[159:128] := SRC1[159:128] - SRC2[159:128]
DEST[191:160] := SRC1[191:160] + SRC2[191:160]
DEST[223:192] := SRC1[223:192] - SRC2[223:192]
DEST[255:224] := SRC1[255:224] + SRC2[255:224]

Intel C/C++ compiler intrinsics#

ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b) VADDSUBPS __m256 _mm256_addsub_ps (__m256 a, __m256 b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general- protection exception (#GP) will be generated.;

SIMD Floating-Point Exceptions#

Overflow, Underflow, Invalid, Precision, Denormal.

Other Exceptions#

See Table 2-19, "Type 2 Class Exception Conditions."

ADOX -- Unsigned Integer Addition of Two Operands With Overflow Flag

Opcode/ Op/ 64/32bit CPUID Description Instruction

                      En Mode           Feature

Support Flag

F3 0F 38 F6 /r RM V/V ADX Unsigned addition of r32 with OF, r/m32 to r32, writes OF. ADOX r32, r/m32

F3 REX.w 0F 38 F6 /r RM V/N.E. ADX Unsigned addition of r64 with OF, r/m64 to r64, writes OF. ADOX r64, r/m64

Description#

Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a generalpurpose register, whereas the source operand can be a general-purpose register or memory location. The state of OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the unsigned addition of the operands.

The ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with a carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).

This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode.

In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.

ADOX executes normally either inside or outside a transaction region. Note: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A.

Operation#

IF OperandSize is 64-bit

    THEN OF:DEST[63:0] := DEST[63:0] + SRC[63:0] + OF;
    ELSE OF:DEST[31:0] := DEST[31:0] + SRC[31:0] + OF;
FI;

Flags affected#

OF is updated based on result. CF, SF, ZF, AF, and PF flags are unmodified.

Intel C/C++ compiler intrinsics#

unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);

SIMD Floating-Point Exceptions#

None.

ADOX -- Unsigned Integer Addition of Two Operands With Overflow Flag

Exceptions

Sources

• This instruction in the Intel manual
• Latency and throughput per microarchitecture