CPUID

CPU Identification

stableVMJITAOTinstruction

Encodings

Measured cost

Description#

The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode.

CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The instruction's output is dependent on the contents of the EAX register upon execution and, in some cases, ECX.

Chapter 21, "Processor Identification and Feature Determination," in Volume 1 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual provides CPUID leaf information and shows information returned, depending on the initial value loaded into the EAX and ECX registers.

CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed. Although the CPUID instruction provides serialization, it is not the preferred method on newer processors that support the SERIALIZE instruction. See "Serializing Instructions" in Chapter 11 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A for more details.

Execution of CPUID causes a VM exit when executed in VMX non-root operation. See Chapter 27, "Virtual Machine Control Structures," of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3C for more details.

IA-32 architecture compatibility#

CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.

Operation#

IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;
(* Note that for some leaf values in EAX, the subleaf value in ECX is ignored. *)
(* Note that for invalid CPUID leaves and subleaves, the output values returned in EAX, EBX, ECX, and EDX are "Reserved" *)
(* Refer to Volume 1, Chapter 21 for details surrounding CPUID_INFO() *)
(EAX, EBX, ECX, EDX) := CPUID_INFO(EAX, ECX)

Flags affected#

None.

CPUID leaves#

CHAPTER 21

When writing software intended to run on Intel processors, it is necessary to identify the type of processor present in a system and the processor features that are available to an application. The CPUID instruction, known as CPU Identification, was introduced with the Intel(R) Pentium processor to query the processor's information name space for its identity and supported features. Logically, the CPUID name space comprises a series of nodes indexed by leaf (using the input value of EAX) and in some cases further indexed by sub-leaf (using the input value of ECX). The value of a queried node is returned in EAX, EBX, ECX, and EDX. Note that not all leaves have sub-leaf indexing and the input ECX value will be ignored in those cases. The full description of CPUID can be found in Chapter 3 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A. All references to "MAX_LEAF" throughout this chapter are used as an abbreviation of "CPUID.00H:EAX.MAX_LEAF".

21.1 IMPORTANT CONSIDERATIONS WHEN USING THE CPUID INSTRUCTION#

This section outlines additional factors to consider when using the CPUID instruction.

21.1.1 Guidelines for Using the CPUID Instruction#

Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction returns the family, model, and (for some processors) a brand string for the processor that executes the instruction. It also indicates the features that are present in the processor and gives information about the processor's caches and TLB. The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID instruction will cause the invalid opcode exception (#UD) if executed on a processor that does not support it. To obtain processor identification information, a source operand value is placed in the EAX register to select the type of information to be returned. When the CPUID instruction is executed, selected information is returned in the EAX, EBX, ECX, and EDX registers. The following guidelines are among the most important and should always be followed when using the CPUID instruction to determine available features:

• Always begin by testing for the "GenuineIntel," message in the EBX, EDX, and ECX registers when the CPUID

instruction is executed with EAX equal to 0. If the processor is not genuine Intel, the feature identification flags may have different meanings than are described in Intel documentation.

• Test feature identification flags individually and do not make assumptions about undefined bits.

21.1.2 Identification of Earlier Processors#

The CPUID instruction is not available in earlier Intel processors up through the earlier Intel 486 processors. For these processors, several other architectural features can be exploited to identify the processor. The settings of bits 12 and 13 (IOPL), 14 (NT), and 15 (reserved) in the EFLAGS register are different for Intel's 32-bit processors than for the Intel 8086 and Intel 286 processors. By examining the settings of these bits (with the PUSHF/PUSHFD and POPF/POPFD instructions), an application program can determine whether the processor is an 8086, Intel 286, or one of the Intel 32-bit processors:

• 8086 processor -- Bits 12 through 15 of the EFLAGS register are always set. * Intel 286 processor -- Bits 12 through 15 are always clear in real-address mode.

• 32-bit processors -- In real-address mode, bit 15 is always clear and bits 12 through 14 have the last value

loaded into them. In protected mode, bit 15 is always clear, bit 14 has the last value loaded into it, and the IOPL bits depend on the current privilege level (CPL). The IOPL field can be changed only if the CPL is 0. Other EFLAGS register bits that can be used to differentiate between the 32-bit processors:

• Bit 18 (AC) -- Implemented only on the Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors.

The inability to set or clear this bit distinguishes an Intel386 processor from the later IA-32 processors.

• Bit 21 (ID) -- Determines if the processor is able to execute the CPUID instruction. The ability to set and clear

this bit indicates that it is a Pentium 4, Intel Xeon, P6 family, Pentium, or later-version Intel486 processor. To determine whether an x87 FPU or Numeric Processor Extension (NPX) is present in a system, applications can write to the x87 FPU status and control registers using the FNINIT instruction and then verify that the correct values are read back using the FNSTENV instruction. After determining that an x87 FPU or NPX is present, its type can then be determined. In most cases, the processor type will determine the type of FPU or NPX; however, an Intel386 processor is compatible with either an Intel 287 or Intel 387 math coprocessor. The method the coprocessor uses to represent (after the execution of the FINIT, FNINIT, or RESET instruction) indicates which coprocessor is present. The Intel 287 math coprocessor uses the same bit representation for + and -; whereas, the Intel 387 math coprocessor uses different representations for + and -.

21.1.3 CPUID Basic and Extended Range#

The CPUID basic range starts at CPUID.00H and ends at the maximum leaf enumerated in CPUID.00H:EAX.MAX_LEAF[31:0]. The legacy set of CPUID leaves are defined as leaves 00H, 01H, and 02H, which represent the architecture up to and including Pentium II. Processors provided legacy compatibility by limiting the exposed number of leaves to just these legacy leaves by setting IA32_MISC_ENABLE[22] (Limit CPUID Maxval). This is no longer supported on processors that report CPUID.07H.01H:EBX.CPUIDMAXVAL_LIM_RMV[3] as 1; for such processors, IA32_MIS- C_ENABLE[22] cannot be set to 1 to limit the value returned by CPUID.00H:EAX.MAX_LEAF. The extended CPUID range starts at leaf 80000000H and ends at the maximum leaf enumerated in CPUID.80000000H:EAX.MAX_EXTENDED_LEAF[31:0]. Older processors before the Pentium 4 do not support the extended CPUID range and treat bit 31 of CPUID's input EAX value as zero. If a value entered for CPUID.EAX is higher than the maximum input value for basic or extended function for that processor then the data for the highest basic information leaf is returned. Software should not rely on the values returned by the processor outside of the above ranges. The range CPUID.40000000H to CPUID.4FFFFFFFH do not return feature information for the processor. These are allocated for emulation by software.

21.1.4 CPUID Domains#

The fields of each CPUID node are classified into one of several CPUID domains. The fields may be classified separately within a specific node or in aggregate for all the nodes in a leaf or sub-leaf. On a properly configured platform, all logical processors within a CPUID domain return a consistent output value for fields belonging to that domain. As an example, the initial X2APIC ID value returned in CPUID.1FH.00H:EDX[31:0] is classified as being in the Logical Processor Domain because the value is unique for each logical processor in the platform. Whereas, the CLFLUSH Line Size returned in CPUID.00H:EBX[15:8] is classified as Platform Domain because it must be consistent for all logical processor within the entire platform.

• Platform Domain--A properly configured platform would provide consistent values for these CPUID fields for

each logical processor in the platform.

• Package Domain--A properly configured platform provides consistent values for these CPUID fields for each

logical processor within the same processor package. These values however can be different when comparing the values of logical processors on different packages.

• Logical Processor Domain--A properly configured platform can provide different values for these CPUID

fields for each logical processor in the platform. The values contained within these may have their own scope as per a specific shared resource (i.e., cache, hybrid, etc.); in that case, each logical processor may need to be queried to obtain the full platform view of given features.

21.1.5 CPUID Runtime Mutable Fields#

A CPUID field is said to be mutable if it can change during runtime. Such fields are affected by supervisor-mode operations that can affect processor mode, status bits, or privileged registers. Mutable fields that are expected to change dynamically as part of normal operation are shown in the table Table 21-1. Mutable fields that should remain consistent are shown in the table Table 21-2. Note all of the listed controls may not be available on all Intel processors.

Runtime Mutable CPUID Fields Expected to Change During Normal Operation

Runtime Mutable CPUID Fields That Should Remain Consistent

Runtime Mutable CPUID Fields That Should Remain Consistent (Contd.)

21.1.6 CPUID Reserved Fields#

Software must ignore and not rely upon the values returned by reserved fields of a CPUID leaf or sub-leaf because they may have meaning on future processors. Once a previously-reserved field becomes defined, this specification will be updated to reflect that.

21.1.7 CPUID Instruction for Serialization#

Although the CPUID instruction provides serialization, it is not the preferred method on newer processors that support the SERIALIZE instruction, which is enumerated via CPUID.07H.00H:EDX[14]=1. If backward compatibility is required with older processors, use leaf 00H [CPUID.00H] for serialization because it has the lowest latency when executed. See "Serializing Instructions" in Chapter 11 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A for more details.

21.1.8 IA32_BIOS_SIGN_ID Returns Microcode Update Signature#

For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 11 in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

21.2 METHODS FOR RETURNING BRANDING INFORMATION USING CPUID#

Use the following techniques to access branding information: 1. Processor brand string method. 2. Processor brand index; this method uses a software supplied brand string table. These two methods are discussed in the following sections. For methods that are available in early processors, see Section 21.1.2, "Identification of Earlier Processors," of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1.

21.2.1 The Processor Brand String Method#

Figure 21-1 describes the algorithm used for detection of the brand string. Processor brand identification software should execute this algorithm on all Intel 64 and IA-32 processors. This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.

Input: EAX= 0x80000000

CPUID

             IF (EAX & 0x80000000)                   False  Processor Brand

String Not Supported

                 CPUID   True
               Function  Extended

Supported

EAX Return Value = Max. Extended CPUID

Function Index

             IF (EAX Return Value                    True   Processor Brand
                 0x80000004)                                String Supported

OM15194

Figure 21-1. Determination of Support for the Processor Brand String

21.2.2 The Processor Brand Index Method#

The brand index method (introduced with Pentium(R) III Xeon(R) processors) provides an entry point into a brand identification table that is maintained in memory by software. In this table, each brand index is associated with an ASCII brand identification string that identifies the official Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can then use this index to locate the brand identification string for the processor in the brand identification table. The first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead.

Table 21-3 shows brand indices that have identification strings associated with them.

Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

21.3 CPUID LEAVES#

The remainder of this chapter provides CPUID enumeration information for Intel(R) 64 and IA-32 architectures.

CPUID.00H -- Maximum Input for Basic CPUID and Vendor ID

CPUID.00H returns the highest value the CPUID recognizes for returning basic processor information. The value is returned in the EAX register and is processor specific. This leaf is always valid. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 00H Maximum Input for Basic CPUID and Vendor ID

CPUID.01H -- Version and Features

CPUID.01H returns type, family, model, stepping, and feature information. This leaf is valid if MAX_LEAF 01H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 01H Output Registers

Leaf 01H Version and Features Returned in EAX

Processor Type Field

Leaf 01H Version and Features Returned in EBX

EBX[31:24] INITIAL_APIC_ID This number is the 8-bit ID that is assigned to Logical

                                                    the local APIC on the processor during power     Processor

up. This field was introduced in the Penium 4 processor. The 8-bit initial APIC ID in EBX[31:24] is

replaced by the 32-bit x2APIC ID, available in Leaf 0BH and Leaf 1FH.

The Maximum Addressable IDs for logical processors in this package should not be used on platforms that support CPUID leaf 0BH or CPUID leaf 1FH as it can be saturated and incorrect. Modern platforms can have many more processors than can be enumerated or have topology domains with discontinuous APIC ID reservations. To correctly enumerate APIC ID information on modern platforms, use CPUID.0BH or CPUID.1FH.

CPUID.01H:ECX Feature Information

The ECX register of CPUID.01H returns the information shown below. For all feature flags, a 1 indicates that the feature is supported. Software should identify Intel as the vendor to properly interpret feature flags. Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features.

Leaf 01H Version and Features Returned in ECX

ECX[13] CMPXCHG16B If 1, supports this instruction. See the Platform "CMPXCHG8B/CMPXCHG16B--Compare and ECX[14] XTPR_UPDATE_CONTROL Exchange Bytes" section in this chapter for a Platform

                               description.                                        Platform

ECX[15] PERF_CAPABILITIES

                               If 1, supports changing IA32_MISC_ENABLE[bit        Platform

ECX[16] Reserved 23]. ECX[17] PCID Platform

                               If 1, supports the performance and debug            Platform

ECX[18] DCA feature indication MSR Platform

                               IA32_PERF_CAPABILITIES.                             Platform

ECX[19] SSE4_1 Platform ECX[20] SSE4_2 Reserved. Platform ECX[21] X2APIC Platform ECX[22] MOVBE If 1, supports Process-context identifiers and Platform ECX[23] POPCNT software setting CR4.PCIDE to 1.Process- Platform ECX[24] TSC_DEADLINE context identifiers. Logical ECX[25] AESNI If 1, supports the ability to prefetch data from a Processor ECX[26] XSAVE memory mapped device. See CPUID.09H. Platform ECX[27] OSXSAVE If 1, supports SSE4.1. Platform Platform ECX[28] AVX If 1, supports SSE4.2. Platform ECX[29] F16C If 1, supports x2APIC feature. ECX[30] RDRAND ECX[31] Not Used If 1, supports MOVBE instruction.

If 1, supports the POPCNT instruction.

If 1, the processor's local APIC timer supports one-shot operation using a TSC deadline value.

If 1, supports the AESNI instruction extensions.

If 1, supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.

If 1, the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR.

If 1, supports the AVX instruction extensions.

If 1, supports 16-bit floating-point conversion instructions.

If 1, supports RDRAND instruction.

Intel processors always return 0. Allocated for use by software emulation.

CPUID.01H:EDX Feature Information

The EDX register of CPUID.01H returns the information shown below. For all feature flags, a 1 indicates that the feature is supported. Software should identify Intel as the vendor to properly interpret feature flags. Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features.

Leaf 01H Version and Features Returned in EDX

EDX[1] VME If 1, supports Virtual 8086 mode Platform enhancements, including CR4.VME for EDX[2] DE controlling the feature; CR4.PVI for protected Platform

                                                    mode virtual interrupts; software interrupt        Platform

EDX[3] PSE indirection; expansion of the TSS with the Platform

                                                    software indirection bitmap; and EFLAGS.VIF        Platform

EDX[4] TSC and EFLAGS.VIP flags. Platform Platform EDX[5] MSR If 1, supports I/O breakpoints debugging

                                                    extensions, including CR4.DE for controlling the   Platform

EDX[6] PAE feature, and optional trapping of accesses to Platform DR4 and DR5. EDX[7] MCE Platform P If 1, supports page size extensions for large EDX[8] CMPXCHG8B pages of size 4 MByte, including: CR4.PSE for EDX[9] APIC controlling the feature; the defined dirty bit in PDE (Page Directory Entries); optional reserved EDX[10] Reserved bit trapping in CR3; PDEs; and PTEs. EDX[11] SEP If 1, supports the Time Stamp Counter, RDTSC instruction, including CR4.TSD for controlling privilege.

If 1, supports the Model Specific Registers RDMSR and WRMSR Instructions. Some of the MSRs are implementation dependent.

If 1, supports the Physical Address Extension which is for physical addresses greater than 32 bits, including: extended page table entry formats; an extra level in the page translation tables; and 2-MByte pages rather than 4 Mbyte pages.

If 1, supports exception 18 for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the modelspecific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.

If 1, supports the CMPXCHG8B (64 bits) Instruction, implicitly locked and atomic.

If 1, the processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FEE00000H to FEE00FFFH (by default - some processors permit the APIC to be relocated).

Reserved.

If 1 supports the SYSENTER and SYSEXIT Instructions and associated MSRs.

EDX[12] MTRR If 1, supports the Memory Type Range Platform Registers. (The MTRRcap MSR contains feature

bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are

supported.)

EDX[13] PGE If 1, supports the global bit in paging-structure Platform

entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls

this feature.

EDX[14] MCA If 1, supports the Machine Check Architecture Platform

feature. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.

EDX[15] CMOV If 1, supports the Conditional Move Instructions. Platform

If CPUID.01H:EDX.FPU[0] (x87 FPU present) is 1 also, supports the FCOMI and FCMOV instructions.

EDX[16] PAT If 1, supports the Page Attribute Table feature. Platform (This feature augments the Memory Type

Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB

granularity.)

EDX[17] PSE_36 If 1, supports the 36-Bit Page Size Extension Platform

which enables 4-MByte pages addressing physical memory beyond 4 GBytes with 32-bit paging. This feature indicates that upper bits of

the physical address of a 4-MByte page are encoded in bits 20:13 of the page directory entry. Such physical addresses are limited by

MAXPHYADDR and may be up to 40 bits in size.

EDX[18] PSN If 1, supports the 96-bit Processor Serial Platform

Number identification number feature, and the feature is enabled. Available only in Pentium III, see CPUID.03H.

EDX[19] CLFLUSH If 1, supports the CLFLUSH instruction. Platform EDX[20] Reserved EDX[21] DS Reserved.

                   If 1, supports the Debug Store feature which        Platform

provides the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and

processor event-based sampling (PEBS) facilities (see Chapter 19, "Debug, Branch Profile, TSC, and Intel(R) Resource Director

Technology (Intel(R) RDT) Features," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B).

EDX[22] ACPI If 1, supports the Thermal Monitor and Platform Software Controlled Clock Facilities. These are EDX[23] MMX internal MSRs that allow processor temperature Platform EDX[24] FXSR to be monitored and processor performance to Platform be modulated in predefined duty cycles under EDX[25] SSE software control. Platform EDX[26] SSE2 Platform EDX[27] SELF_SNOOP If 1, supports the Intel MMX Technology. Platform Platform EDX[28] HTT If 1, supports the FXSAVE and FXRSTOR

                                                    Instructions, which are fast save and restore of  Platform

EDX[29] TM the floating-point context, and the availability

                                                    of CR4.OSFXSR for an operating system to          Platform

EDX[30] Reserved indicate support of same. EDX[31] PBE If 1, supports SSE.

If 1, supports SSE2.

If 1, supports Self Snoop which is the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.

If 1, the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package. If 0, there is only a single logical processor in the package and software should assume only a single APIC ID is reserved.

If 1, supports the Thermal Monitor feature in which the processor implements the thermal monitor automatic thermal control circuitry (TCC).Thermal Monitor.

Reserved.

If 1, supports the Pending Break Enable feature, which is the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt.

CPUID.02H -- TLB/Cache/Prefetch Information

CPUID.02H returns TLB, cache, and prefetch information.This leaf has been superseded by CPUID.04H for cache enumeration and CPUID.18H for TLB enumeration. These processors will also report new descriptor values of types 0FEh or 0FFh to refer enumerations to CPUID.04H and CPUID.18H. This leaf is valid if MAX_LEAF 02H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 02H TLB/Cache/Prefetch Information

below. Note that the order of descriptors in the EAX, EBX, ECX, and EDX registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache, prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general descriptor type FFH and FEH and not report any byte descriptor of "cache type" or "*TLB type" via CPUID.02H.

Descriptor Type Table 21-12. Encoding of CPUID Leaf 2 Descriptors Value 00H General Cache or TLB Description 01H TLB 02H TLB Null descriptor, this byte contains no information. 03H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries. 04H TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries. 05H TLB Data TLB: 4 KByte pages, 4-way set associative, 64 entries. 06H Cache Data TLB: 4 MByte pages, 4-way set associative, 8 entries. 08H Cache Data TLB1: 4 MByte pages, 4-way set associative, 32 entries. 09H Cache 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size. 0AH Cache 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size. 0BH TLB 1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size. 0CH Cache 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size. 0DH Cache Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries. 0EH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size. 1DH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size. 21H Cache 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size. 22H Cache 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size. 23H Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size. 24H Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector. 25H Cache 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector. 29H Cache 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size. 2CH Cache 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector. 30H Cache 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector. 40H Cache 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size. 41H Cache 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size. 42H Cache No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache. 43H Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size. 44H Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size. 45H Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size. 46H Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size. 47H Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size. 48H Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size. 49H Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size. 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size. 3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H) 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.

4AH Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size.

4BH Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size.

4CH Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size.

4DH Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size.

4EH Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size.

4FH TLB Instruction TLB: 4 KByte pages, 32 entries.

50H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries.

51H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries.

52H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries.

55H TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries.

56H TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries.

57H TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries.

59H TLB Data TLB0: 4 KByte pages, fully associative, 16 entries.

5AH TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries.

5BH TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries.

5CH TLB Data TLB: 4 KByte and 4 MByte pages,128 entries.

5DH TLB Data TLB: 4 KByte and 4 MByte pages,256 entries.

60H Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size.

61H TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries.

63H TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with

1 GByte pages, 4-way set associative, 4 entries.

64H TLB Data TLB: 4 KByte pages, 4-way set associative, 512 entries.

66H Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size.

67H Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size.

68H Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size.

6AH Cache uTLB: 4 KByte pages, 8-way set associative, 64 entries.

6BH Cache DTLB: 4 KByte pages, 8-way set associative, 256 entries.

6CH Cache DTLB: 2M/4M pages, 8-way set associative, 128 entries.

6DH Cache DTLB: 1 GByte pages, fully associative, 16 entries.

70H Cache Trace cache: 12 K-?op, 8-way set associative.

71H Cache Trace cache: 16 K-?op, 8-way set associative.

72H Cache Trace cache: 32 K-?op, 8-way set associative.

76H TLB Instruction TLB: 2M/4M pages, fully associative, 8 entries.

78H Cache 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size.

79H Cache 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7AH Cache 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7BH Cache 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7CH Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7DH Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size.

7FH Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size.

80H Cache 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size.

82H Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size.

83H Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size.

84H Cache 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size.

85H Cache 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size.

86H Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size.

87H Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size.

A0H DTLB DTLB: 4k pages, fully associative, 32 entries.

B0H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries.

B1H TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries.

B2H TLB Instruction TLB: 4KByte pages, 4-way set associative, 64 entries.

B3H TLB Data TLB: 4 KByte pages, 4-way set associative, 128 entries.

B4H TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries.

B5H TLB Instruction TLB: 4KByte pages, 8-way set associative, 64 entries.

B6H TLB Instruction TLB: 4KByte pages, 8-way set associative, 128 entries.

BAH TLB Data TLB1: 4 KByte pages, 4-way associative, 64 entries.

C0H TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries.

C1H STLB Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries.

C2H DTLB DTLB: 2 MByte/4 MByte pages, 4-way associative, 16 entries.

C3H STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte

pages, 4-way, 16 entries.

C4H DTLB DTLB: 2 MByte/ 4MByte pages, 4-way associative, 32 entries.

CAH STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries.

D0H Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size.

D1H Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size.

D2H Cache 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size.

D6H Cache 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size.

D7H Cache 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size.

D8H Cache 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size.

DCH Cache 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size.

DDH Cache 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size.

DEH Cache 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size.

E2H Cache 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size.

E3H Cache 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size.

E4H Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size.

EAH Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size.

EBH Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size.

ECH Cache 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size.

F0H Prefetch 64-Byte prefetching.

F1H Prefetch 128-Byte prefetching.

FEH General CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and

other address translation parameters.

FFH General CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache

parameters.

Example 21-1. Example of Cache and TLB Interpretation

The first member of the family of Pentium 4 processors returns the following information about caches and TLBs when the CPUID executes with an input value of 2: EAX 66 5B 50 01H EBX 0H ECX 0H EDX 00 7A 70 00H Which means: The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored. The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register contains valid 1-byte descriptors. * Bytes 1, 2, and 3 of register EAX indicate that the processor has:

-- 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages. -- 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages. -- 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size. The descriptors in registers EBX and ECX are valid, but contain NULL descriptors. Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has: -- 00H - NULL descriptor. -- 70H - Trace cache: 12 K-op, 8-way set associative. -- 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size. -- 00H - NULL descriptor.

CPUID.03H -- Processor Serial Number

CPUID.03H returns the processor serial number, if available. Processor serial number (PSN) is not supported in the Pentium 4 processor or later. This leaf is valid if MAX_LEAF 03H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Register Field Name Table 21-13. Leaf 03H Processor Serial Number Domain EAX[31:0] Reserved Package EBX[31:0] Reserved Description Package ECX[31:0] PSN_31_0 Reserved. EDX[31:0] PSN_63_32 Reserved.

Bits 00-31 of 96-bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)

Bits 32-63 of 96-bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)

CPUID.04H -- Deterministic Cache Parameters

CPUID.04H returns the deterministic cache parameters for each cache level. This leaf is valid if CPUID.04H.00H:EAX[4:0] <> 0 and MAX_LEAF 04H. The sub-leaves are enumerated until sub-leaf n returns 0 in EAX[4:0]. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-leaf n returns EAX[4:0] as 0.

Leaf 04H Deterministic Cache Parameters

ECX[31:0] NUM_SETS Number of sets. Logical EDX[0] NOT_LWR_CACHE_FLUSH Add one to the return value to get the result. Processor Logical EDX[1] INCLUSIVE_CACHE 0 = WBINVD/INVD from threads sharing this Processor EDX[2] COMPLEX_CACHE_INDEXING cache acts upon lower level caches for threads

                                                    sharing this cache.                                Logical
                                                    1 = WBINVD/INVD is not guaranteed to act upon      Processor
                                                    lower level caches of non-originating threads      Logical
                                                    sharing this cache.                                Processor

EDX[31:3] Reserved 0 = Cache is not inclusive of lower cache levels. 1 = Cache is inclusive of lower cache levels.

0 = Direct mapped cache. 1 = A complex function is used to index the cache, potentially using all address bits.

Reserved.

When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0. Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the cache type field is 0. This Cache Size in Bytes = (Ways + 1) (Partitions + 1) (Line_Size + 1) (Sets + 1) = (EBX[31:22] + 1) (EBX[21:12] + 1) (EBX[11:0] + 1) (ECX + 1) The CPUID.04H also reports data that can be used to derive the topology of processor cores in a physical package on legacy processors. This information is constant for all valid index values. Software can query the raw data reported by executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm on processors that do not enumerate either CPUID.0BH or CPUID.1FH as described in Chapter 10, "Multiple- Processor Management," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

CPUID.05H -- MONITOR and MWAIT Features

CPUID.05H returns the MONITOR and MWAIT feature information. This leaf is valid if MAX_LEAF 05H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 05H MONITOR and MWAIT Features

CPUID.06H -- Thermal and Power Management Features

CPUID.06H returns information about thermal and power management features. This leaf is valid if MAX_LEAF 06H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 06H Thermal and Power Management Features

EAX[23] THREAD_DIRECTOR If 1, supports Intel(R) Thread Director. Platform

                                     IA32_HW_FEEDBACK_CHAR and                          Platform

EAX[31:24] Reserved IA32_HW_FEEDBACK_THREAD_CONFIG MSRs Platform EBX[3:0] DTS_NUM_INT_THRESHOLDS are supported if set. Platform EBX[31:4] Reserved Reserved. Platform ECX[0] HW_FEEDBACK_CAP Package Number of Interrupt Thresholds in Digital ECX[2:1] Reserved Thermal Sensor. Package ECX[3] ENERGY_PERF_BIAS Logical

                                     Reserved.                                          Processor

ECX[7:4] Reserved ECX[15:8] HW_FEEDBACK_NUM_CLASSES If 1, supports IA32_MPERF and IA32_APERF which provide a measure of delivered processor ECX[31:16] Reserved performance (since last reset of the counters), EDX[7:0] HW_FEEDBACK_CAPS as a percentage of the expected processor performance when running at the TSC EDX[11:8] HW_FEEDBACK_TABLE_SIZE frequency.

EDX[15:12] Reserved Reserved. EDX[31:16] HW_FEEDBACK_TABLE_INDEX If 1, supports performance-energy bias preference and a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).

Reserved.

Number of Intel(R) Thread Director classes supported by the processor. Information for that many classes is written into the Intel Thread Director Table by the hardware.

Reserved.

Bitmap of supported hardware feedback interface capabilities. 0 = If 1, supports performance capability reporting. 1 = If 1, supports energy efficiency capability reporting. 2-7 = Reserved. Bits 0 and 1 will always be set together.

Enumerates the size of the hardware feedback interface structure in number of 4 KB pages. Add one to the return value to get the result.

Reserved.

Index (starting at 0) of this logical processor's row in the hardware feedback interface structure. Note that on some parts the index may be same for multiple logical processors. On some parts the indices may not be contiguous, i.e., there may be unused rows in the hardware feedback interface structure.

Details around these features are described in Chapter 16, "Power and Thermal Management," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.

CPUID.07H -- Structured Extended Feature Flags

CPUID.07H returns structured extended feature flags enumeration information. The sub-sections of Section provide leaf 07H information. This leaf is valid if MAX_LEAF 07H. The maximum sub-leaf value for ECX is specified in CPUID.07H.00H.EAX[31:0] MAX_SUBLEAF. * If ECX contains an invalid Sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.07H.00H -- Structured Extended Feature Flags Main Sub-Leaf

CPUID.07H.00H returns the maximum input value of the highest leaf 07H sub-leaf; and EBX, ECX, and EDX contain information of extended feature flags.

Leaf 07H Sub-Leaf (ECX=0) Output Registers

Leaf 07H.00H Structured Extended Feature Flags Returned in EAX

Leaf 07H.00H Structured Extended Feature Flags Returned in EBX

EBX[6] FDP_EXCPTN_ONLY If 1, the x87 FPU Data Pointer is updated only Platform on x87 exceptions. EBX[7] SMEP Platform If 1, supports Supervisor-Mode Execution EBX[8] BMI2 Prevention. Platform EBX[9] ENH_REP_MOVSB_STOSB Platform EBX[10] INVPCID If 1, supports the BMI2 instructions. Platform

EBX[11] RTM If 1, supports Enhanced REP MOVSB/STOSB. Platform

EBX[12] RDT_M If 1, supports INVPCID instruction for system Platform software that manages process-context EBX[13] FCS_FDS_DEPRECATION identifiers. Platform EBX[14] MPX Platform If 1, supports the Restricted Transactional EBX[15] RDT_A Memory instruction set. Platform

EBX[16] AVX512F If 1, supports Intel(R) Resource Director Platform EBX[17] AVX512DQ Technology (Intel(R) RDT) Monitoring capability. Platform EBX[18] RDSEED Platform EBX[19] ADX If 1, deprecates FPU CS and FPU DS values. Platform EBX[20] SMAP Platform If 1, supports Intel(R) Memory Protection EBX[21] AVX512_IFMA Extensions. Platform EBX[22] Reserved EBX[23] CLFLUSHOPT If 1, supports Intel(R) Resource Director Platform EBX[24] CLWB Technology (Intel(R) RDT) Allocation capability. Platform EBX[25] INTEL_PROC_TRACE Platform EBX[26] AVX512PF If 1, supports the AVX512F instructions. Platform

EBX[27] AVX512ER If 1, supports the AVX512DQ instructions. Platform

EBX[28] AVX512CD If 1, supports the RDSEED instruction. Platform EBX[29] SHA Platform If 1, supports the ADX instructions. EBX[30] AVX512BW Platform EBX[31] AVX512VL If 1, supports Supervisor-Mode Access Platform Prevention and the CLAC/STAC instructions.

If 1, supports the AVX512_IFMA instructions.

Reserved.

If 1, supports the CLFLUSHOPT instruction.

If 1, supports the CLWB instruction.

If 1, supports Intel(R) Processor Trace.

If 1, supports the AVX512PF instructions. (Intel(R) Xeon PhiTM only.)

If 1, supports the AVX512ER instructions. (Intel(R) Xeon PhiTM only.)

If 1, supports the AVX512CD instructions.

If 1, supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) SHA Extensions).

If 1, supports the AVX512BW instructions.

If 1, supports the AVX512VL instructions.

CPUID.07H.00H:ECX Extended Feature Flags Information

The ECX register of CPUID.07H.00H returns the information shown below.

Leaf 07H.00H Structured Extended Feature Flags Returned in ECX

ECX[0] PREFETCHWT1 If 1, supports the PREFETCHWT1 instruction. Platform ECX[1] AVX512_VBMI (Intel(R) Xeon PhiTM only.) ECX[2] UMIP ECX[3] PKU If 1, supports the AVX512_VBMI instructions. Platform ECX[4] OSPKE If 1, supports user-mode instruction prevention. Platform ECX[5] WAITPKG ECX[6] AVX512_VBMI2 If 1, supports protection keys for user-mode Platform ECX[7] CET_SS pages.

                                                    If 1, the OS has set CR4.PKE to enable           Logical

Processor protection keys and the RDPKRU/WRPKRU instructions.

                                                    If 1, supports the TPAUSE, UMONITOR, and         Platform

UMWAIT instructions.

If 1, supports the AVX512_VBMI2 instructions. Platform

                                                    If 1, supports CET shadow stack features.        Platform

Processors that set this bit define bits 1:0 of the IA32_U_CET and IA32_S_CET MSRs.

Enumerates support for the following MSRs: IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP,

and IA32_PL0_SSP.

ECX[8] GFNI If 1, supports the GFNI instruction set. Platform ECX[9] VAES If 1 and Intel AVX supported, supports the VEX- Platform ECX[10] VPCLMULQDQ encoded AES instruction set.

ECX[11] AVX512_VNNI If 1 and Intel AVX supported, supports the Platform ECX[12] AVX512_BITALG VPCLMULQDQ instruction. ECX[13] TME_EN If 1, supports the AVX512_VNNI instructions. Platform

If 1, supports the AVX512_BITALG instructions. Platform

                                                    If 1, the following MSRs are supported:          Platform

IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.

ECX[14] AVX512_VPOPCNTDQ If 1, supports the AVX512_VPOPCNTDQ Platform instructions.

ECX[15] Reserved Reserved. ECX[16] LA57 If 1, supports 57-bit linear addresses and five- Platform level paging.

ECX[21:17] MPX_MAWAU The value of MAWAU used by the BNDLDX and Platform BNDSTX instructions in 64-bit mode.

ECX[22] RDPID If 1, RDPID and the IA32_TSC_AUX MSR are Platform available.

ECX[23] KEY_LOCKER If 1, supports Key Locker. Platform ECX[24] BUS_LOCK_DETECT ECX[25] CLDEMOTE If 1, indicates support for OS bus-lock detection. Platform ECX[26] Reserved ECX[27] MOVDIRI If 1, supports cache line demote. Platform ECX[28] MOVDIR64B ECX[29] ENQCMD Reserved.

                                                    If 1, supports the MOVDIRI instruction.          Platform

                                                    If 1, supports the MOVDIR64B instruction.        Platform

                                                    If 1, supports Enqueue Stores.                   Platform

ECX[30] SGX_LC If 1, supports SGX Launch Configuration. Platform ECX[31] PKS Platform If 1, supports protection keys for supervisormode pages.

CPUID.07H.00H:EDX Extended Feature Flags Information

The EDX register of CPUID.07H.00H returns the information shown below.

Leaf 07H.00H Structured Extended Feature Flags Returned in EDX

EDX[21] Reserved Reserved. Platform EDX[22] AMX_BF16 Platform

                                                    If 1, supports tile computational operations on     Platform

EDX[23] AVX512_FP16 bfloat16 numbers. Platform Platform EDX[24] AMX_TILE If 1, supports the FP16 data type with AVX512 EDX[25] AMX_INT8 instructions. Platform Platform EDX[26] IBRS_IBPB If 1, supports tile architecture. Platform Platform EDX[27] SPEC_CTRL_ST_PREDICTORS If 1, supports tile computational operations on

                                                    8-bit integers.                                     Platform

EDX[28] L1D_FLUSH_INTERFACE If 1, supports indirect branch restricted EDX[29] ARCH_CAPABILITIES speculation (IBRS) and the indirect branch EDX[30] CORE_CAPABILITIES predictor barrier (IBPB). Processors that set this bit support the IA32_SPEC_CTRL MSR and the EDX[31] SPEC_CTRL_SSBD IA32_PRED_CMD MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and IA32_PRED_CMD[0] (IBPB).

If 1, supports single thread indirect branch predictors (STIBP). Processors that set this bit support the IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] (STIBP).

If 1, supports L1D_FLUSH. Processors that set this bit support the IA32_FLUSH_CMD MSR. They allow software to set IA32_FLUSH_CMD[0] (L1D_- FLUSH).

If 1, supports the IA32_ARCH_CAPABILITIES MSR.

If 1, supports the IA32_CORE_CAPABILITIES MSR. IA32_CORE_CAPABILITIES is an architectural MSR that enumerates model-specific features. A bit being set in this MSR indicates that a model specific feature is supported; software must still consult CPUID family/model/stepping to determine the behavior of the enumerated feature as features enumerated in IA32_CORE_CAPABILITIES may have different behavior on different processor models. Some of these features may have behavior that is consistent across processor models (and for which consultation of CPUID family/model/stepping is not necessary); such features are identified explicitly where they are documented in this manual.

If 1, supports Speculative Store Bypass Disable (SSBD). Processors that set this bit support the IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[2] (SSBD).

CPUID.07H.01H -- Structured Extended Feature Sub-Leaf 1

CPUID.07H.01H:EAX Extended Feature Information

The EAX register of CPUID.07H.01H returns the information shown below.

Leaf 07H.01H Structured Extended Feature Flags Returned in EAX

EAX[31] Reserved Reserved.

CPUID.07H.01H:EBX Extended Feature Information

The EBX register of CPUID.07H.01H returns the information shown below.

Leaf 07H.01H Structured Extended Feature Flags Returned in EBX

Leaf 07H.01H Structured Extended Feature Flags Returned in ECX

Leaf 07H.01H Structured Extended Feature Flags Returned in EDX

EDX[13:11] Reserved Reserved. Platform EDX[14] PREFETCHI Platform EDX[16:15] Reserved If 1, supports the PREFETCHIT0/1 instructions. Platform EDX[17] UIRET_UIF

                                   Reserved.                                                        Platform

EDX[18] CET_SSS Platform

                                   If 1, UIRET sets UIF to the value of bit 1 of the                Platform

EDX[19] AVX10 RFLAGS image loaded from the stack. Platform

EDX[21:20] Reserved If 1, indicates that an operating system can EDX[22] SEC-TEE-ATTESTATION enable supervisor shadow stacks as long as it EDX[23] MWAIT ensures that a supervisor shadow stack cannot become prematurely busy due to page faults EDX[24] SLSM (see Section 17.2.3 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, EDX[31:25] Reserved Volume 1). When emulating the CPUID instruction, a virtual-machine monitor (VMM) should return this bit as 1 only if it ensures that VM exits cannot cause a guest supervisor shadow stack to appear to be prematurely busy. Such a VMM could set the "prematurely busy shadow stack" VM-exit control and use the additional information that it provides.

If 1, supports the Intel(R) AVX10 instructions and indicates the presence of CPUID.24H, which enumerates the version number.

Reserved.

N/A

If 1, MWAIT is supported (even if CPUID.01H:ECX.MONITOR[3] is enumerated as 0).

Static LSM is supported on this platform. If set, IA32_INTEGRITY_STATUS (0x2DC) is available for software use.

Reserved.

CPUID.07H.02H -- Structured Extended Feature Sub-Leaf 2

CPUID.07H.02H returns the structured extended feature information contained in the sub-sections of this section.

CPUID Output Table 21-26. Leaf 07H Sub-Leaf (ECX=2) Output Registers Registers Description

EAX[31:0] Reserved EBX[31:0] Reserved Reserved ECX[31:0] Extended Feature Information (see "CPUID.07H.02H:EDX--Extended Feature Information")

EDX[31:0]

CPUID.07H.02H:EDX Extended Feature Information

The EDX register of CPUID.07H.02H returns the information shown below.

CPUID.07H.02H Extended Feature Information Provided in EDX1

CPUID.08H -- Reserved

This leaf is reserved.

Register Field Name Table 21-28. Leaf 08H Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.09H -- Direct Cache Access Information

CPUID.09H returns information about Direct Cache Access capabilities. This leaf is valid if CPUID.01H:ECX.DCA[18] = 1 and MAX_LEAF 09H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 09H Direct Cache Access Information

CPUID.0AH -- Architectural Performance Monitoring

CPUID.0AH returns information about support for architectural performance monitoring capabilities. This leaf is valid if CPUID.0AH:EAX[7:0] (Version ID) > 0 and MAX_LEAF 0AH. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 0AH Architectural Performance Monitoring

ECX[31:0] FIXED_CTR_MASK Supported fixed counters bit mask. Fixed- Platform

                                                    function performance counter 'i' is supported if          Platform

EDX[4:0] NUM_FIXED_CTR bit 'i' is 1 (first counter index starts at zero). It is Platform

                                                    recommended to use the following logic to                 Platform

EDX[12:5] FIXED_CTR_WIDTH determine if a Fixed Counter is supported:

                                                    FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i);        Platform

EDX[14:13] Reserved EDX[15] ANYTHREAD_DEPRECATION Number of contiguous fixed-function performance counters starting from 0 (if EDX[19:16] SLOTS_PER_CYC Version ID > 1).

EDX[31:20] Reserved Bit width of fixed-function performance counters (if Version ID > 1).

Reserved.

Starting with Architectural Performance Monitoring Version 5, this field indicates that a processor supports AnyThread mode deprecation. If this field is set, software can choose to ignore guidelines in "AnyThread Counting and Software Evolution" of Chapter 21, "Performance Monitoring," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B

If this field is non-zero, it represents the number of Top-down Microarchitecture Analysis (TMA) slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots. If this field is zero, IA32_FIXED_CTR3 should be used to determine the total number of slots.

Reserved.

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover the programming facilities and the architectural performance events available in the processor. The details are described in Chapter 21, "Performance Monitoring," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3C.

CPUID.0BH -- Extended Topology

CPUID.0BH returns information about Extended Topology. CPUID.1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of leaf 1FH before using leaf 0BH. * This leaf is valid if CPUID.0BH.00H:EBX[15:0] <> 0 and MAX_LEAF 0BH.

• When the leaf is invalid, CPUID.0BH.00H:ECX.DOMAIN_TYPE[15:8] will report the Domain Type ID as Invalid (0). The sub-leaves are enumerated until sub-leaf n returns 0 in EBX[15:0]. If ECX contains an invalid sub-leaf index, EAX/EBX return 0. Sub-leaf index n+1 is invalid if sub-leaf n returns EBX[15:0] as 0.

CPUID.0BH -- ECX >= 0

Leaf 0BH Extended Topology

ECX[15:8] DOMAIN_TYPE This field provides an identification value which Platform indicates the domain shown in the table. ECX[31:16] Reserved Although domains are ordered, their assigned Logical EDX[31:0] X2APIC_ID identification values are not and software Processor should not depend on it. Note that enumeration values of 0 and 3-255 are reserved.

Reserved.

The X2APIC ID of this logical processor.

The sub-leaves of CPUID.0BH describe an ordered hierarchy of logical processors starting from the smallest-scoped domain of a Logical Processor (sub-leaf index 0) to the Core domain (sub-leaf index 1) to the largest-scoped domain (the last valid sub-leaf index) that is implicitly subordinate to the unenumerated highest-scoped domain of the processor package (socket). The details of each valid domain is enumerated by a corresponding sub-leaf. Details for a domain include its type and how all instances of that domain determine the number of logical processors and x2 APIC ID partitioning at the next higher-scoped domain. The ordering of domains within the hierarchy is fixed architecturally as shown below. For a given processor, not all domains may be relevant or enumerated; however, the logical processor and core domains are always enumerated. For two valid sub-leaves N and N+1, sub-leaf N+1 represents the next immediate higher-scoped domain with respect to the domain of sub-leaf N for the given processor. If sub-leaf index "N" returns an invalid domain type in ECX[15:08] (00H), then all sub-leaves with an index greater than "N" also return an invalid domain type. A sub-leaf returning an invalid domain always returns 0 in EAX and EBX.

Hierarchy of Valid Domain Enumerations in CPUID.0BH:ECX[15:8]

CPUID.0CH -- Reserved

Register Field Name Table 21-33. Leaf 0CH Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.0DH -- Processor Extended State

CPUID.0DH returns a bit-vector representation of all processor state extensions that are supported in the processor and storage size requirements of the XSAVE/XRSTOR area. This leaf is valid if CPUID.01H:ECX.XSAVE[26] = 1 and MAX_LEAF 0DH. Sub-leafs 0 and 1 are always valid; consult them to determine which other sub-leafs are present as described in "CPUID.0DH.n, n>01H--State Sub-Leaves".

CPUID.0DH.00H -- Processor Extended State Main Sub-Leaf

CPUID.0DH.00H returns the processor extended state information.

Leaf 0DH.00H Processor Extended State

CPUID.0DH.01H -- Feature and Supervisor State Sub-Leaf

CPUID.0DH.01H returns feature and supervisor state information.

Leaf 0DH.01H Processor Extended State

// For each supported feature indicated by sub-leaf 0 and 1, read the size and offset sub-leaf // For j= 2 to 62

If (CPUID.0DH.00H:<EDX:EAX>[j] == 1 or // Use 64-bit value of EDX:EAX CPUID.0DH.01H:<EDX:ECX>[j] == 1) // Use 64-bit value of EDX:ECX Read(CPUID.0DH.j) // Examine the size and offset.

END IF END FOR

Leaf 0DH.SUB-LEAVES Processor Extended State

CPUID.0EH -- Reserved

This leaf is reserved.

Register Field Name Table 21-37. Leaf 0EH Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.0FH -- Intel(R) Resource Director Technology (Intel(R) RDT) Monitoring

CPUID.0FH returns information for the Intel Resource Director Technology Monitoring capabilities. As described below, software uses the bit vector returned in EDX by sub-leaf 00H to determine the available resource types (ResID) that can be monitored. This information is necessary for software to program the IA32_PQR_ASSOC and IA32_QM_EVTSEL MSRs such that Quality-of-Service data can be read afterwards from the IA32_QM_CTR MSR. This leaf is valid if CPUID.07H.00H:EBX.RDT_M[12] = 1 and MAX_LEAF 0FH. If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n 1) is only valid when (CPUID.0FH.00H:EDX[n] == 1).

CPUID.0FH.00H -- Intel(R) RDT Monitoring Main Sub-Leaf

CPUID.0FH.00H returns information about Intel RDT Monitoring.

Leaf 0FH.00H Intel(R) Resource Director Technology (Intel(R) RDT) Monitoring

Leaf 0FH.01H Intel(R) Resource Director Technology (Intel(R) RDT) Monitoring

EAX[31:11] Reserved Reserved. Platform EBX[31:0] CONV_FACTOR

                          Factor used to convert from reported           Platform

ECX[31:0] MAX_RMID_L3 IA32_QM_CTR value to derived occupancy Platform

                          metric (bytes) and Memory Bandwidth            Platform

EDX[0] CMT_L3_OCCUP Monitoring (MBM) metrics. Platform EDX[1] MBM_L3_TOTAL EDX[2] MBM_L3_LOCAL Maximum range (zero-based) of RMID of this EDX[31:3] Reserved resource type.

If 1, supports L3 occupancy monitoring.

If 1, supports L3 total bandwidth monitoring.

If 1, supports L3 local bandwidth monitoring.

Reserved.

CPUID.10H -- Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

CPUID.10H returns information for Intel Resource Director Technology Allocation. This leaf is valid when CPUID.07H.00H:EBX.RDT_A[15] = 1. As described below, software uses the bit vector returned in EBX by subleaf 00H to determine the available QoS Enforcement (allocation) resource types that are supported in the processor. This information is necessary for software to configure each class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n. This leaf is valid if CPUID.07H.00H:EBX.RDT_A[15] = 1 and MAX_LEAF 10H. If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n 1) is only valid when (CPUID.10H.00H:EBX[n] == 1).

CPUID.10H.00H -- Intel(R) RDT Allocation Main Sub-Leaf

CPUID.10H.00H returns information about Intel RDT Allocation.

Leaf 10H.00H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

Leaf 10H.01H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

ECX[0] Reserved Reserved. Platform ECX[1] CAT_L3_NONCPU Platform ECX[2] CAT_L3_CDP If 1, supports L3 CAT for non-CPU agents. Platform

ECX[3] CAT_L3_NONCONTIG If 1, supports L3 Code and Data Prioritization Platform Technology. ECX[31:4] Reserved EDX[15:0] CAT_L3_MAX_CLOS If 1, supports non-contiguous capacity bitmasks. The bits that are set in the various EDX[31:16] Reserved IA32_L3_MASK_n registers do not have to be contiguous.

Reserved.

Highest Class of Service (COS) number supported for this ResID.

Reserved.

CPUID.10H.02H -- L2 Cache Allocation Technology

CPUID.10H.ResID=2 returns information about L2 Cache Allocation Technology.

Leaf 10H.02H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

Leaf 10H.03H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

EBX[31:0] Reserved Reserved. Platform ECX[0] PER_THREAD_MBA Per-thread MBA controls are supported. Platform ECX[1] Reserved Reserved. Platform ECX[2] MBA_LINEAR If 1, the response of the delay values is linear. ECX[31:3] Reserved Reserved. EDX[15:0] MBA_MAX_CLOS Highest Class of Service (COS) number supported for this ResID. EDX[31:16] Reserved Reserved.

CPUID.10H.05H -- Cache Bandwidth Allocation

Leaf 10H.05H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

Leaf 10H.06H Intel(R) Resource Director Technology (Intel(R) RDT) Allocation

CPUID.11H -- Reserved

This leaf is reserved.

Register Field Name Table 21-46. Leaf 11H Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.12H -- Intel(R) Software Guard Extensions (Intel(R) SGX) Capability

CPUID.12H returns information about Intel(R) SGX capabilities. More details can be found in Chapter 35, "Introduction to Intel(R) Software Guard Extensions," and Chapter 36, "Enclave Access Control and Data Structures," of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D. This leaf is valid when CPUID.07H.00H:EBX.SGX[2] = 1 and MAX_LEAF 12H. If the leaf is valid, sub-leaf 00H and 01H are always valid. Sub-leaf n (n 2) is only valid when CPUID.12H.n:EAX[3:0] != 0.

CPUID.12H.00H -- Intel(R) SGX Main Sub-Leaf

CPUID.12H.00H returns information about Intel(R) SGX capabilities. It is only valid when CPUID.07H.00H:EBX.SGX = 1.

Leaf 12H.00H Intel(R) Software Guard Extensions (Intel(R) SGX) Capability

Leaf 12H.01H Intel(R) Software Guard Extensions (Intel(R) SGX) Capability

EAX[31:0] ECREATE_SECS_ATTRIBUTES_31_0 Reports the valid bits of Platform

                                            SECS.ATTRIBUTES[31:0] that software can set     Platform

EBX[31:0] ECREATE_SECS_ATTRIBUTES_63_32 with ECREATE. Platform Platform ECX[31:0] ECREATE_SECS_ATTRIBUTES_95_64 Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set EDX[31:0] ECREATE_SECS_ATTRIBUTES_127_96 with ECREATE.

Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.

Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.

The definition of the attributes can be found in Section 36.7.1, "ATTRIBUTES," of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D

CPUID.12H -- n2 - Intel(R) SGX Enclave Page Cache

CPUID.12H with ECX2 returns information about Intel(R) SGX Enclave Page Cache and is supported if CPUID.07H.00H:EBX.SGX = 1. For sub-leaves where ECX2, the definition of EAX[31:4], EBX, ECX, and EDX depends on the sub-leaf type listed below.

Sub-Leaf Encoding Type EAX[3:0] = 0000b (Invalid)

This sub-leaf is invalid. EDX:ECX:EBX:EAX return 0.

CPUID.12H -- Sub-Leaf Encoding Type EAX[3:0] = 0001b

This sub-leaf enumerates an EPC section with EDX:ECX, EBX:EAX defined as follows.

Leaf 12H.SUB-LEAF ENCODING TYPE EAX[3:0] = 0001B Intel(R) Software Guard Extensions (Intel(R) SGX)

ECX[3:0] EPC_SECTION_PROPERTY EPC Section Property Encoding Definitions, as Platform follows:

                                                    0000b  All bits in EDX:ECX are enumerated as

0.

                                                    0001b  This section has confidentiality,

integrity, and replay protection.

                                                    0010b  This section has confidentiality

protection only.

0011b - This section has confidentiality and integrity protection. All other encodings are reserved.

ECX[11:4] Reserved Reserved. ECX[31:12] EPC_SECTION_SIZE_31_12 Bits 31:12 of the size of the corresponding EPC Platform section within the Processor Reserved Memory.

EDX[19:0] EPC_SECTION_SIZE_51_32 Bits 51:32 of the size of the corresponding EPC Platform section within the Processor Reserved Memory.

EDX[31:20] Reserved Reserved.

CPUID.13H -- Reserved

This leaf is reserved.

Register Field Name Table 21-50. Leaf 13H Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.14H -- Intel(R) Processor Trace (Intel(R) PT)

CPUID.14H returns information about Intel(R) Processor Trace (PT). CPUID.14H.00H returns information about Intel Processor Trace extensions. CPUID.14H.n (n > 0 and less than the number of non-zero bits in CPUID.14H.00H:EAX) returns information about packet generation in Intel Processor Trace. For more details on Intel PT, see Chapter 34, "Intel(R) Processor Trace," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D. This leaf is valid when CPUID.07H.00H:EBX.INTEL_PROC_TRACE[25] = 1 and MAX_LEAF 14H. The maximum sub-leaf value for ECX is specified in CPUID.14H.00H.EAX[31:0] MAX_SUBLEAF. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.14H.00H -- Intel(R) PT Main Sub-Leaf

CPUID.14H.00H returns information about Intel Processor Trace extensions.

Leaf 14H.00H Intel(R) Processor Trace (Intel(R) PT)

EBX[9] PTTT If 1, Processor Trace Trigger Tracing (PTTT) is Platform

                                       supported.                                         Platform

EBX[31:10] Reserved ECX[0] TOPAOUT Reserved. Platform

ECX[1] MENTRY If 1, supports that tracing can be enabled with Platform

                                       IA32_RTIT_CTL.ToPA = 1, hence utilizing the        Platform

ECX[2] SNGL_RNG_OUT ToPA output scheme; Logical ECX[3] TRACE_TRANSPORT_SUBSYSTEM IA32_RTIT_OUTPUT_BASE and Processor IA32_RTIT_OUPUT_MASK_PTRS MSRs can be ECX[30:4] Reserved accessed. ECX[31] LIP If 1, supports that ToPA tables can hold any EDX[31:0] Reserved number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.

If 1, supports the Single-Range Output scheme.

If 1, supports the output to Trace Transport subsystem.

Reserved.

If 1, the generated packets which contain IP payloads contain LIP. If 0, the generated packets which contain IP payloads contain Effective IP. Trace segments using a flat memory model will generate the same information regardless of how a logical processor reports this value since LIP=EIP.

Reserved.

CPUID.14H.01H -- Feature Information Sub-Leaf

CPUID.14H.01H returns information about packet generation in Intel Processor Trace.

Leaf 14H.01H Intel(R) Processor Trace (Intel(R) PT)

ECX[15] TRIGGER_DR_MATCH If 1, trigger input DR match is supported. Platform ECX[31:16] Reserved Reserved. EDX[31:0] Reserved Reserved.

CPUID.15H -- Time Stamp Counter and Nominal Core Crystal Clock

CPUID.15H returns information about the Time Stamp Counter and the Nominal Core Crystal Clock. This leaf is valid if MAX_LEAF 15H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 15H Time Stamp Counter and Nominal Core Crystal Clock

CPUID.16H -- Processor Frequency Information

CPUID.16H returns information about processor frequency information. Data is returned from this interface in accordance with the processor's specification and does not reflect actual values. Suitable use of this data includes the display of processor information in like manner to the processor brand string and for determining the appropriate range to use when displaying processor information e.g. frequency history graphs. The returned information should not be used for any other purpose as the returned information does not accurately correlate to information / counters returned by other processor interfaces. While a processor may support the Processor Frequency Information leaf, fields that return a value of zero are not supported. This leaf is valid if MAX_LEAF 16H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 16H Processor Frequency Information

CPUID.17H -- System-on-Chip Vendor Attribute

CPUID.17H returns System-on-Chip vendor attribute information. This leaf is valid if CPUID.17H.00H:EAX[31:0] (MaxSOCID_Index) 3 and MAX_LEAF 17H. The maximum sub-leaf value for ECX is specified in CPUID.17H.00H.EAX[31:0] MaxSOCID_Index. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.17H.00H -- Main Sub-Leaf

CPUID.17H.00H returns System-on-Chip vendor attribute information.

Leaf 17H.00H System-on-Chip Vendor Attribute

Leaf 17H.01H System-on-Chip Vendor Attribute

Leaf 17H.02H System-on-Chip Vendor Attribute

ECX[31:0] VENDOR_BRAND_STRING_BYTES_24_to_27 SOC Vendor Brand String. UTF-8 encoded string. Platform EDX[31:0] VENDOR_BRAND_STRING_BYTES_28_to_31 SOC Vendor Brand String. UTF-8 encoded string. Platform

CPUID.17H.03H -- Vendor Brand String Sub-Leaf (Bytes 32 to 47)

Leaf 17H.03H System-on-Chip Vendor Attribute

Leaf 17H.M>MAXSOCID_INDEX--RESERVED SUB-LEAVES System-on-Chip Vendor Attribute

CPUID.18H -- Deterministic Address Translation Parameters

CPUID.18H returns information about the Deterministic Address Translation Parameters. Each sub-leaf enumerates a different address translation structure. This leaf is valid if CPUID.18H.00H:EAX[31:0] <> 0 and MAX_LEAF 18H. The maximum sub-leaf value for ECX is specified in CPUID.18H.00H.EAX[31:0] MAX_SUBLEAF. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0. Valid sub-leaves do not need to be contiguous or in any particular order. A valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or than a valid sub-leaf of a higher or lower-level structure.

CPUID.18H.00H -- Main Sub-Leaf

Deterministic Address Translation Parameters Main Leaf

Leaf 18H.00H Deterministic Address Translation Parameters

Leaf 18H.ECX >= 1 Deterministic Address Translation Parameters

EDX[4:0] TYPE 00000b: Null (indicates this Sub-leaf is not Logical

                                                    valid).                                           Processor

EDX[7:5] LEVEL_NUM 00001b: Data TLB.

                                                    00010b: Instruction TLB.                          Logical

EDX[8] FULLY_ASSOC 00011b: Unified TLB.1 Processor

                                                    00100b: Load Only TLB. Hit on loads; fills on     Logical

EDX[13:9] Reserved both loads and stores. Processor EDX[25:14] MAX_LP_ADDRESSABLE_IDS 00101b: Store Only TLB. Hit on stores; fill on Logical

                                                    stores.                                           Processor

All other encodings are reserved. EDX[31:26] Reserved Some unified TLBs will allow a single TLB entry to satisfy data read/write and instruction fetches. Others will require separate entries (e.g., one loaded on data read/write and another loaded on an instruction fetch). See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for details of a particular product.

Translation cache level (starts at 1).

Fully associative structure.

Reserved.

Maximum number of addressable IDs for logical processors sharing this translation cache. Add one to the return value to get the result.

Reserved.

CPUID.19H -- Key Locker

CPUID.19H returns Key Locker information. This leaf is valid if CPUID.07H.00H:ECX.KEY_LOCKER[23] = 1 and MAX_LEAF 19H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 19H Key Locker

CPUID.1AH -- Native Model ID Enumeration

CPUID.1AH returns Native Model ID information. This leaf exists on all logical processors in a hybrid package, it may also be present in other processor configurations. This leaf is valid if CPUID.1AH.00H:EAX[31:0] <> 0 and MAX_LEAF 1AH. The only valid sub-leaf is 0 and ECX must be set to 0.

Leaf 1AH Native Model ID Enumeration

CPUID.1BH -- PCONFIG Information

CPUID.1BH -- Output Registers Format for All Sub-Leaves

CPUID.1BH returns information for PCONFIG capabilities. This information is enumerated in sub-leaves selected by the value of ECX (starting with 0). This leaf is valid if CPUID.07H.00H:EDX.PCONFIG[18] = 1 and MAX_LEAF 1BH. Sub-leaves are enumerated until sub-leaf n, where EAX[11:0] returns 0.

Register Field Name Table 21-64. Leaf 1BH PCONFIG Information Domain EAX[11:0] SUB_LEAF_TYPE Platform EAX[31:12] Reserved Description EBX[31:0] Reserved 0 (Invalid) ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

Each sub-leaf of CPUID.1BH enumerates its sub-leaf type in EAX. If a sub-leaf type is 0, the sub-leaf is invalid and zero is returned in EBX, ECX, and EDX. In this case, all subsequent sub-leaves (selected by larger input values of ECX) are also invalid. The only valid sub-leaf type currently defined is 1, indicating that the sub-leaf enumerates target identifiers for the PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a valid target identifier of the PCONFIG instruction (any value of zero should be ignored). The only target identifier currently defined is 1, indicating TME-MK. See the "PCONFIG--Platform Configuration" instruction in Chapter 4 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2B, for more information.

CPUID.1BH.OUTPUT REGISTERS FOR SUB-LEAVE TYPE TARGET IDENTIFIER (1) -- Output Registers for Sub-Leave Type Target Identifier (1)

Leaf 1BH.OUTPUT REGISTERS FOR SUB-LEAVE TYPE TARGET IDENTIFIER (1) PCONFIG Information

CPUID.1CH -- Last Branch Records (LBR) Information

CPUID.1CH returns information about architectural Last Branch Records (LBR). For details on LBR, see Chapter 20, "Last Branch Records," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. This leaf is valid if CPUID.07H.00H:EDX.ARCH_LBRS[19] = 1 and MAX_LEAF 1CH. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 1CH Last Branch Records (LBR) Information

CPUID.1DH -- Tile Information

CPUID.1DH returns information about tile architecture and tile palette 1 (see Chapter 19, "Programming with Intel(R) Advanced Matrix Extensions," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1). This leaf is valid if CPUID.07H.00H:EDX.AMX_TILE[24] = 1 and MAX_LEAF 1DH. The maximum sub-leaf value for ECX is specified in CPUID.1DH.00H.EAX[31:0] max_palette. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.1DH.00H -- Tile Information Main Sub-Leaf

CPUID.1DH.00H returns the tile architecture information.

Register Field Name Table 21-67. Leaf 1DH.00H Tile Information Domain EAX[31:0] MAX_PALETTE Platform EBX[31:0] Reserved Description ECX[31:0] Reserved Highest numbered palette sub-leaf. Value = 1. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.1DH.01H -- Tile Palette 1

CPUID.1DH.01H returns tile palette information.

Leaf 1DH.01H Tile Information

CPUID.1EH -- TMUL Information

CPUID.1EH returns information about TMUL capabilities (see Chapter 19, "Programming with Intel(R) Advanced Matrix Extensions," in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1). This leaf is valid if CPUID.07H.00H:EDX.AMX_TILE[24] = 1 and MAX_LEAF 1EH. The only valid sub-leaf is 0 and ECX must be set to 0.

CPUID.1EH.00H -- TMUL Information Main Leaf

TMUL Main Leaf Information

Register Field Name Table 21-69. Leaf 1EH.00H TMUL Information Domain EAX[31:0] Reserved EBX[7:0] TMUL_MAXK Description Platform EBX[23:8] TMUL_MAXN Reserved. Platform EBX[31:24] Reserved tmul_maxk (rows or columns). Value = 16. ECX[31:0] Reserved tmul_maxn (column bytes). Value = 64. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.1FH -- V2 Extended Topology

CPUID.1FH returns information about V2 Extended Topology. CPUID.1FH is a preferred superset to leaf 0BH. Intel recommends using leaf 1FH when available rather than leaf 0BH and ensuring that any leaf 0BH algorithms are updated to support leaf 1FH. * This leaf is valid if CPUID.1FH.00H:EBX[15:0] <> 0 and MAX_LEAF 1FH.

• When the leaf is invalid, CPUID.1FH.00H:ECX.DOMAIN_TYPE[15:8] will report the Domain Type ID as Invalid (0). The sub-leaves are enumerated until sub-leaf n returns 0 in EBX[15:0]. If ECX contains an invalid sub-leaf index, EAX/EBX return 0. Sub-leaf index n+1 is invalid if sub-leaf n returns EBX[15:0] as 0.

CPUID.1FH -- ECX >= 0

Leaf 1FH V2 Extended Topology

ECX[7:0] LEVEL_NUM The input ECX sub-leaf index. Platform ECX[15:8] DOMAIN_TYPE Platform This field provides an identification value which ECX[31:16] Reserved indicates the domain as shown in the table. Logical EDX[31:0] X2APIC_ID Although domains are ordered, their assigned Processor identification values are not and software should not depend on it. (For example, if a new domain between core and module is specified, it will have an identification value higher than 5.) See the table below for the current list of valid enumerations. Note that enumeration values of 0 and 7-255 are reserved.

Reserved.

The x2APIC ID of the current logical processor is always valid and does not vary with the subleaf index in ECX.

The sub-leaves of CPUID.1FH describe an ordered hierarchy of logical processors starting from the smallest scoped domain of a Logical Processor (sub-leaf index 0) to the Core domain (sub-leaf index 1) to the largest scoped domain (the last valid sub-leaf index) that is implicitly subordinate to the unenumerated highest-scoped domain of the processor package (socket). The details of each valid domain is enumerated by a corresponding sub-leaf. Details for a domain include its type and how all instances of that domain determine the number of logical processors and x2 APIC ID partitioning at the next higher-scoped domain. The ordering of domains within the hierarchy is fixed architecturally as shown below. For a given processor, not all domains may be relevant or enumerated; however, the logical processor and core domains are always enumerated. As an example, a processor may report an ordered hierarchy consisting only of "Logical Processor," "Core," and "Die." For two valid sub-leaves N and N+1, sub-leaf N+1 represents the next immediate higher-scoped domain with respect to the domain of sub-leaf N for the given processor. If sub-leaf index "N" returns an invalid domain type in ECX[15:08] (00H), then all sub-leaves with an index greater than "N" also return an invalid domain type. A sub-leaf returning an invalid domain always returns 0 in EAX and EBX.

Hierarchy of Valid Domain Enumerations in CPUID.1FH:ECX[15:8]

CPUID.20H -- Processor History Reset Information

CPUID.20H returns information about processor history reset when CPUID.07H.01H:EAX.HRESET[22] = 1. This leaf is valid if CPUID.07H.01H:EAX.HRESET[22] = 1 and MAX_LEAF 20H. The maximum sub-leaf value for ECX is specified in CPUID.20H.00H.EAX[31:0] MAX_SUBLEAF. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.20H.00H -- Processor History Reset Sub-leaf

Leaf 20H.00H Processor History Reset Information

CPUID.21H -- Unimplemented

Does not return feature information for the processor. Allocated for use by TDX modules; see Intel(R) Trust Domain Extensions (Intel(R) TDX) Module Base Architecture Specification. Software emulating CPUID should not change the information returned for this leaf.

CPUID.22H -- Reserved

This leaf is reserved.

Register Field Name Table 21-73. Leaf 22H Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.23H -- Architectural Performance Monitoring Extended

CPUID.23H returns architectural performance monitoring extended information. This leaf is valid if CPUID.07H.01H:EAX.ARCH_PERFMON_EXT[8] = 1 and MAX_LEAF 23H. The sub-leaves of this leaf are enumerated by a bitmask specified in CPUID.23H.00H.EAX[31:0] SUBLEAF_MASK. The bit numbers of set bits in the bitmask represent valid sub-leaf indexes. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index is invalid if the index as a bit number is clear in the Available Sub-Leaf Mask or is greater than 31.

CPUID.23H.00H -- Main Sub-Leaf

Leaf 23H.00H Architectural Performance Monitoring Extended

Leaf 23H.01H Architectural Performance Monitoring Extended

CPUID.23H.02H -- Bitmap of Auto Counter Reload Sub-Leaf

Leaf 23H.02H Architectural Performance Monitoring Extended

Leaf 23H.03H Architectural Performance Monitoring Extended

EAX[10] FRONTEND If 1, supports architectural index 10 Logical Processor EAX[11] RETIRING If 1, supports architectural index 11 Logical EAX[12] LBR_INSERTS If 1, supports architectural index 12 Processor

                                                    Reserved.                                        Logical
                                                    Reserved.                                        Processor

Reserved. EAX[31:13] Reserved Reserved. EBX[31:0] Reserved ECX[31:0] Reserved EDX[31:0] Reserved

CPUID.23H.04H -- PEBS Capabilities

Leaf 23H.04H Architectural Performance Monitoring Extended

CPUID.23H.05H -- Arch PEBS GP and Fixed Counters supported

Leaf 23H.05H Architectural Performance Monitoring Extended

CPUID.24H -- Converged Vector ISA

When CPUID.24H, the processor returns Intel AVX10 converged vector ISA information. This leaf is supported when CPUID.07H.01H:EDX.AVX10[19] = 1. This leaf is valid if CPUID.07H.01H:EDX.AVX10[19] = 1 and MAX_LEAF 24H. The maximum sub-leaf value for ECX is specified in CPUID.24H.00H.EAX[31:0] MAX_SUBLEAF. * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.

CPUID.24H.00H -- Converged Vector ISA Main Sub-Leaf

Leaf 24H.00H Converged Vector ISA

CPUID.27H -- Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Monitoring

CPUID.27H returns information for the Intel Resource Director Technology Monitoring capabilities with asymmetric topology. As described below, software uses the bit vector returned in EDX by sub-leaf 00H to determine the available resource types (ResID) that can be monitored. This information is necessary for software to program the IA32_PQR_ASSOC and IA32_QM_EVTSEL MSRs such that Quality-of-Service data can be read afterwards from the IA32_QM_CTR MSR. This leaf is valid if CPUID.07H.01H:ECX.RDT_M_ASYM[0] = 1 and MAX_LEAF 27H. If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n 1) is only valid when (CPUID.27H.00H:EDX[n] == 1). * This leaf must be read on each logical processor to determine the support on each processor.

CPUID.27H.00H -- Intel(R) RDT Asymmetric Monitoring Main Sub-Leaf

CPUID.27H.00H returns information about Intel RDT Monitoring Asymmetric.

Leaf 27H.00H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Monitoring

Leaf 27H.01H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Monitoring

EAX[9] IO_RDT_CMT If 1, indicates the presence of non-CPU agent Logical

                                                    supporting Intel RDT CMT.                      Processor

EAX[10] IO_RDT_MBM If 1, indicates the presence of non-CPU agent Logical

                                                    supporting Intel RDT MBM support.              Processor

EAX[31:11] Reserved Reserved. EBX[31:0] CONV_FACTOR Factor used to convert from reported Logical

                                                    IA32_QM_CTR value to derived occupancy         Processor

ECX[31:0] MAX_RMID_L3 metric (bytes) and Memory Bandwidth EDX[0] CMT_L3_OCCUP Monitoring (MBM) metrics. Logical EDX[1] MBM_L3_TOTAL Maximum range (zero-based) of RMID of this Processor EDX[2] MBM_L3_LOCAL resource type. Logical EDX[31:3] Reserved If 1, supports L3 occupancy monitoring. Processor Logical

                                                    If 1, supports L3 total bandwidth monitoring.  Processor

Logical

                                                    If 1, supports L3 local bandwidth monitoring.  Processor

Reserved.

CPUID.28H -- Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

CPUID.28H returns information for Intel Resource Director Technology Allocation with asymmetric topology. This leaf is valid when CPUID.07H.01H:ECX.RDT_A_SYM[1] = 1. As described below, software uses the bit vector returned in EBX by subleaf 00H to determine the available QoS Enforcement (allocation) resource types that are supported in the processor. This information is necessary for software to configure each class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n. This leaf is valid if CPUID.07H.01H:ECX.RDT_A_SYM[1] = 1 and MAX_LEAF 28H. If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n 1) is only valid when (CPUID.28H.00H:EBX[n] == 1).

CPUID.28H.00H -- Intel(R) RDT Asymmetric Allocation Main Sub-Leaf

CPUID.28H.00H returns information about Intel RDT Allocation Asymmetric.

Leaf 28H.00H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

Leaf 28H.01H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

EBX[31:0] CAT_L3_CONTENTION Bit-granular map of isolation/contention of Logical ECX[0] Reserved allocation units. Processor ECX[1] CAT_L3_NONCPU ECX[2] CAT_L3_CDP If 1, supports L3 CAT for non-CPU agents. Logical ECX[3] CAT_L3_NONCONTIG Processor

                                                    N/A                                             Logical

ECX[31:4] Reserved Processor EDX[15:0] CAT_L3_MAX_CLOS If 1, supports L3 Code and Data Prioritization Logical

                                                    Technology.                                     Processor

                                                    If 1, supports non-contiguous capacity          Logical
                                                    bitmasks. The bits that are set in the various  Processor

IA32_L3_MASK_n registers do not have to be EDX[31:16] Reserved contiguous.

Reserved.

Highest Class of Service (COS) number supported for this ResID.

Reserved.

CPUID.28H.02H -- Asymmetric L2 Cache Allocation Technology

CPUID.28H.ResID=2 returns information about Asymmetric L2 Cache Allocation Technology.

Leaf 28H.02H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

Leaf 28H.03H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

EAX[11:0] MBA_MAX Reports the maximum MBA throttling value Logical

                                            supported for the corresponding ResID. Add          Processor

EAX[31:12] Reserved one to the return value to get the result. EBX[31:0] Reserved Reserved. Logical ECX[0] PER_THREAD_MBA Reserved. Processor Per-thread MBA controls are supported. ECX[1] Reserved Logical ECX[2] MBA_LINEAR Reserved. Processor If 1, the response of the delay values is linear. ECX[31:3] Reserved Logical EDX[15:0] MBA_MAX_CLOS Reserved. Processor Highest Class of Service (COS) number EDX[31:16] Reserved supported for this ResID. Reserved.

CPUID.28H.05H -- Asymmetric Cache Bandwidth Allocation

Leaf 28H.05H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

Leaf 28H.06H Intel(R) Resource Director Technology (Intel(R) RDT) Asymmetric Allocation

EAX[1] PACKAGE_ENABLE If 1, supports physical processor package Platform enable of RP through the IA32_RESOURCE EAX[31:2] Reserved PRIORITY_PKG MSR. EBX[31:0] Reserved ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved.

Reserved.

Reserved.

CPUID.80000000H -- Maximum Input Value for Extended Function CPUID Information

CPUID.80000000H returns the highest value the processor recognizes for returning extended processor information. The value is returned in the EAX register and is processor specific. This leaf is supported starting with Pentium 4. Processors prior to Pentium 4 treat bit 31 as 0, and this leaf returns the values from CPUID.00H. * This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000000H Maximum Input Value for Extended Function CPUID Information

CPUID.80000001H -- Extended Processor Signature and Feature Bits

CPUID.80000001H returns information about extended processor signature and features bits. This leaf is valid if MAX_EXTENDED_LEAF 80000001H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000001H Extended Processor Signature and Feature Bits

CPUID.80000002H -- Processor Brand String (Bytes 0 to 15)

CPUID.80000002H returns information about the Processor Brand String. For additional details on Processor Brand String, see Section 21.2, "Methods for Returning Branding Information Using CPUID." This leaf is valid if MAX_EXTENDED_LEAF 80000002H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000002H Processor Brand String (Bytes 0 to 15)

CPUID.80000003H -- Processor brand string (Bytes 16 to 31)

CPUID.80000003H returns information about the Processor Brand String. For additional details on Processor Brand String, see Section 21.2, "Methods for Returning Branding Information Using CPUID." This leaf is valid if MAX_EXTENDED_LEAF 80000003H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000003H Processor brand string (Bytes 16 to 31)

CPUID.80000004H -- Processor brand string (Bytes 32 to 47)

CPUID.80000004H returns information about the Processor Brand String. For additional details on Processor Brand String, see Section 21.2, "Methods for Returning Branding Information Using CPUID." This leaf is valid if MAX_EXTENDED_LEAF 80000004H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000004H Processor brand string (Bytes 32 to 47)

CPUID.80000005H -- Reserved

This leaf is reserved and returns all zeroes.

Register Field Name Table 21-94. Leaf 80000005H Reserved Domain EAX[31:0] Reserved EBX[31:0] Reserved Description ECX[31:0] Reserved Reserved. EDX[31:0] Reserved Reserved. Reserved. Reserved.

CPUID.80000006H -- Extended Function CPUID Information

CPUID.80000006H returns Extended Function CPUID information. The preferred method to enumerate caching information description>is to use CPUID.04H--Deterministic Cache Parameters. This leaf is valid if MAX_EXTENDED_LEAF 80000006H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX

Leaf 80000006H Extended Function CPUID Information

L2 Associativity Field Encodings

CPUID.80000007H -- Extended Function CPUID Information 1

CPUID.80000007H returns Extended Function CPUID information. This leaf is valid if MAX_EXTENDED_LEAF 80000007H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000007H Extended Function CPUID Information 1

CPUID.80000008H -- Extended Function CPUID Information 2

CPUID.80000008H returns Extended Function CPUID information. This leaf is valid if MAX_EXTENDED_LEAF 80000008H. This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Leaf 80000008H Extended Function CPUID Information 2

Exceptions

Sources

• This instruction in the Intel manual
• Latency and throughput per microarchitecture