Vesta
English
Source code

PCLMULQDQ

Carry-Less Multiplication Quadword

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F 3A 44 /r ibPCLMULQDQ xmm1, xmm2/m128, imm8AValidValidPerforms carry-less multiplication of one quadword of xmm1 by one quadword of xmm2/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm1 and xmm2/m128 should be used.
VEX.128.66.0F3A.WIG 44 /r ibVPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8BValidValidPerforms carry-less multiplication of one AVX quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.
VEX.256.66.0F3A.WIG 44 /r /ibVPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8BValidValidFor each 128-bit lane, performs two carry-less AVX multiplications of one quadword of ymm2 by one quadword of ymm3/m256, stores the two 128-bit results in ymm1. The immediate is used to determine which quadword in each 128-bit lane of ymm2 and ymm3/m256 should be used.
EVEX.128.66.0F3A.WIG 44 /r /ibVPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8CValidValidPerforms carry-less multiplication of one (AVX512VL OR AVX10.1) quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.
EVEX.256.66.0F3A.WIG 44 /r /ibVPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8CValidValidFor each 128-bit lane, performs two carry-less (AVX512VL OR AVX10.1) multiplications of one quadword of ymm2 by one quadword of ymm3/m256, stores the two 128-bit results in ymm1. The immediate is used to determine which quadword in each 128-bit lane of ymm2 and ymm3/m256 should be used.
EVEX.512.66.0F3A.WIG 44 /r /ibVPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8CValidValidFor each 128-bit lane, performs two carry-less (AVX512F OR AVX10.1) multiplications of one quadword of zmm2 by one quadword of zmm3/m512, stores the four 128-bit results in zmm1. The immediate is used to determine which quadword in each 128-bit lane of zmm2 and zmm3/m512 should be used.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8immediate byte after the instruction

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8immediate byte after the instruction

C

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8 lecturaimmediate byte after the instruction

Tupla: Full Mem

Measured cost

Loading measurements from arch-data...

Description

Performs packed carry-less multiplication of quadword pairs. XMM versions perform a single multiply of a pair of

quadwords. YMM versions perform two packed multiplies of pairs of quadwords. ZMM versions perform four packed multiplies of pairs of quadwords. Bits 4 and 0 are used to select which 64-bit half of each operand to use according to Table 4-14, other bits of the immediate byte are ignored.

The EVEX encoded form of this instruction does not support memory fault suppression.

PCLMULQDQ Quadword Selection of Immediate Byte

Imm[4]Imm[0]PCLMULQDQ Operation
0CL_MUL( SRC21[63:0], SRC1[63:0] )

Pseudo-Op and PCLMULQDQ Implementation Imm8 Encoding

Pseudo-OpImm8 Encoding
PCLMULLQLQDQ xmm1, xmm20000_0000B
PCLMULHQLQDQ xmm1, xmm20000_0001B
PCLMULLQHQDQ xmm1, xmm20001_0000B
PCLMULHQHQDQ xmm1, xmm20001_0001B

Operation

define PCLMUL128(X,Y):             // helper function

   FOR i := 0 to 63:

   TMP [ i ] := X[ 0 ] and Y[ i ]

   FOR j := 1 to i:

           TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])

   DEST[ i ] := TMP[ i ]

   FOR i := 64 to 126:

   TMP [ i ] := 0

   FOR j := i - 63 to 63:

           TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])

   DEST[ i ] := TMP[ i ]

   DEST[127] := 0;

   RETURN DEST                     // 128b vector


PCLMULQDQ (SSE Version)
IF imm8[0] = 0:

    TEMP1 := SRC1.qword[0]
ELSE:

    TEMP1 := SRC1.qword[1]
IF imm8[4] = 0:

    TEMP2 := SRC2.qword[0]
ELSE:

    TEMP2 := SRC2.qword[1]
DEST[127:0] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:128] (Unmodified)

VPCLMULQDQ (128b and 256b VEX Encoded Versions)
(KL,VL) = (1,128), (2,256)
FOR i= 0 to KL-1:

    IF imm8[0] = 0:
          TEMP1 := SRC1.xmm[i].qword[0]

    ELSE:
          TEMP1 := SRC1.xmm[i].qword[1]

    IF imm8[4] = 0:
          TEMP2 := SRC2.xmm[i].qword[0]

    ELSE:
          TEMP2 := SRC2.xmm[i].qword[1]

    DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:VL] := 0

VPCLMULQDQ (EVEX Encoded Version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i = 0 to KL-1:

    IF imm8[0] = 0:
          TEMP1 := SRC1.xmm[i].qword[0]

    ELSE:
          TEMP1 := SRC1.xmm[i].qword[1]

    IF imm8[4] = 0:
          TEMP2 := SRC2.xmm[i].qword[0]

    ELSE:
          TEMP2 := SRC2.xmm[i].qword[1]

    DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

(V)PCLMULQDQ __m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int) VPCLMULQDQ __m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);
VPCLMULQDQ __m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, "Type 4 Class Exception Conditions," additionally:

#UD               If VEX.L = 1.

EVEX-encoded: See Table 2-52, "Type E4NF Class Exception Conditions."

Sources