Vesta
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Source code

SARX, SHLX, SHRX

Shift Without Affecting Flags

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.LZ.F3.0F38.W0 F7 /rSARX r32a, r/m32, r32bRMVValidValidShift r/m32 arithmetically right with count specified in r32b and load into r32a.
VEX.LZ.66.0F38.W0 F7 /rSHLX r32a, r/m32, r32bRMVValidValidShift r/m32 logically left with count specified in r32b and load into r32a.
VEX.LZ.F2.0F38.W0 F7 /rSHRX r32a, r/m32, r32bRMVValidValidShift r/m32 logically right with count specified in r32b and load into r32a.
VEX.LZ.F3.0F38.W1 F7 /rSARX r64a, r/m64, r64bRMVValidNot encodableShift r/m64 arithmetically right with count specified in r64b and load into r64a.
VEX.LZ.66.0F38.W1 F7 /rSHLX r64a, r/m64, r64bRMVValidNot encodableShift r/m64 logically left with count specified in r64b and load into r64a.
VEX.LZ.F2.0F38.W1 F7 /rSHRX r64a, r/m64, r64bRMVValidNot encodableShift r/m64 logically right with count specified in r64b and load into r64a.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RMV

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. vex.vvvv lecturaVEX prefix, vvvv field (inverted)

Measured cost

Loading measurements from arch-data...

Description

Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in the second source operand (the third operand). The result is written to the destination operand (the first operand).

The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting.

The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit locations).

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.

SARX,SHRX, and SHLX instructions do not update flags.

Operation

TEMP := SRC1;
IF VEX.W1 and CS.L = 1
THEN

    countMASK := 3FH;
ELSE

    countMASK := 1FH;
FI
COUNT := SRC2 AND countMASK;

DO WHILE (COUNT  0)
    IF instruction is SHLX
          THEN
                TEMP := TEMP *2;


         ELSE IF instruction is SHRX

         THEN

                TEMP := TEMP /2; //unsigned divide

         ELSE   // SARX

                TEMP := TEMP /2; // signed divide, round toward negative infinity

    FI;

    COUNT := COUNT - 1;

OD

DEST := TEMP;

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, "Type 13 Class Exception Conditions."

Sources