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Source code

VPSHRDV

Concatenate and Variable Shift Packed Data Right Logical

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W1 72 /rVPSHRDVW xmm1{k1}{z}, xmm2, xmm3/m128AValidValidConcatenate xmm1 and xmm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m128 OR AVX10.1 into xmm1.
EVEX.256.66.0F38.W1 72 /rVPSHRDVW ymm1{k1}{z}, ymm2, ymm3/m256AValidValidConcatenate ymm1 and ymm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m256 OR AVX10.1 into ymm1.
EVEX.512.66.0F38.W1 72 /rVPSHRDVW zmm1{k1}{z}, zmm2, zmm3/m512AValidValidConcatenate zmm1 and zmm2, extract result OR AVX10.1 shifted to the right by value in zmm3/m512 into zmm1.
EVEX.128.66.0F38.W0 73 /rVPSHRDVD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcstBValidValidConcatenate xmm1 and xmm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m128 OR AVX10.1 into xmm1.
EVEX.256.66.0F38.W0 73 /rVPSHRDVD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstBValidValidConcatenate ymm1 and ymm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m256 OR AVX10.1 into ymm1.
EVEX.512.66.0F38.W0 73 /rVPSHRDVD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcstBValidValidConcatenate zmm1 and zmm2, extract result OR AVX10.1 shifted to the right by value in zmm3/m512 into zmm1.
EVEX.128.66.0F38.W1 73 /rVPSHRDVQ xmm1{k1}{z}, xmm2, xmm3/m128/m64bcstBValidValidConcatenate xmm1 and xmm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m128 OR AVX10.1 into xmm1.
EVEX.256.66.0F38.W1 73 /rVPSHRDVQ ymm1{k1}{z}, ymm2, ymm3/m256/m64bcstBValidValidConcatenate ymm1 and ymm2, extract result AND AVX512VL) shifted to the right by value in xmm3/m256 OR AVX10.1 into ymm1.
EVEX.512.66.0F38.W1 73 /rVPSHRDVQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcstBValidValidConcatenate zmm1 and zmm2, extract result OR AVX10.1 shifted to the right by value in zmm3/m512 into zmm1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full Mem

B

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

Concatenate packed data, extract result shifted to the right by variable value. This instruction supports memory fault suppression.

Operation

VPSHRDVW DEST, SRC2, SRC3
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:

    IF MaskBit(j) OR *no writemask*:
          DEST.word[j] := concat(SRC2.word[j], DEST.word[j]) >> (SRC3.word[j] & 15)

    ELSE IF *zeroing*:
          DEST.word[j] := 0

    *ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

VPSHRDVD DEST, SRC2, SRC3
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:

    IF SRC3 is broadcast memop:
          tsrc3 := SRC3.dword[0]

    ELSE:
          tsrc3 := SRC3.dword[j]

    IF MaskBit(j) OR *no writemask*:
          DEST.dword[j] := concat(SRC2.dword[j], DEST.dword[j]) >> (tsrc3 & 31)

    ELSE IF *zeroing*:
          DEST.dword[j] := 0

    *ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

VPSHRDVQ DEST, SRC2, SRC3
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:

    IF SRC3 is broadcast memop:
          tsrc3 := SRC3.qword[0]

    ELSE:
          tsrc3 := SRC3.qword[j]

    IF MaskBit(j) OR *no writemask*:
          DEST.qword[j] := concat(SRC2.qword[j], DEST.qword[j]) >> (tsrc3 & 63)

    ELSE IF *zeroing*:
          DEST.qword[j] := 0

    *ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPSHRDVQ __m128i _mm_shrdv_epi64(__m128i, __m128i, __m128i);
VPSHRDVQ __m128i _mm_mask_shrdv_epi64(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVQ __m128i _mm_maskz_shrdv_epi64(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVQ __m256i _mm256_shrdv_epi64(__m256i, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_mask_shrdv_epi64(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_maskz_shrdv_epi64(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVQ __m512i _mm512_shrdv_epi64(__m512i, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_mask_shrdv_epi64(__m512i, __mmask8, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_maskz_shrdv_epi64(__mmask8, __m512i, __m512i, __m512i);
VPSHRDVD __m128i _mm_shrdv_epi32(__m128i, __m128i, __m128i);
VPSHRDVD __m128i _mm_mask_shrdv_epi32(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVD __m128i _mm_maskz_shrdv_epi32(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVD __m256i _mm256_shrdv_epi32(__m256i, __m256i, __m256i);
VPSHRDVD __m256i _mm256_mask_shrdv_epi32(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVD __m256i _mm256_maskz_shrdv_epi32(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVD __m512i _mm512_shrdv_epi32(__m512i, __m512i, __m512i);
VPSHRDVD __m512i _mm512_mask_shrdv_epi32(__m512i, __mmask16, __m512i, __m512i);
VPSHRDVD __m512i _mm512_maskz_shrdv_epi32(__mmask16, __m512i, __m512i, __m512i);
VPSHRDVW __m128i _mm_shrdv_epi16(__m128i, __m128i, __m128i);
VPSHRDVW __m128i _mm_mask_shrdv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVW __m128i _mm_maskz_shrdv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVW __m256i _mm256_shrdv_epi16(__m256i, __m256i, __m256i);
VPSHRDVW __m256i _mm256_mask_shrdv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHRDVW __m256i _mm256_maskz_shrdv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHRDVW __m512i _mm512_shrdv_epi16(__m512i, __m512i, __m512i);
VPSHRDVW __m512i _mm512_mask_shrdv_epi16(__m512i, __mmask32, __m512i, __m512i);
VPSHRDVW __m512i _mm512_maskz_shrdv_epi16(__mmask32, __m512i, __m512i, __m512i);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, "Type E4 Class Exception Conditions."

Sources