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Source code

MULX

Unsigned Multiply Without Affecting Flags

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
VEX.LZ.F2.0F38.W0 F6 /rMULX r32a, r32b, r/m32RVMValidValidUnsigned multiply of r/m32 with EDX without affecting arithmetic flags.
VEX.LZ.F2.0F38.W1 F6 /rMULX r64a, r64b, r/m64RVMValidNot encodableUnsigned multiply of r/m64 with RDX without affecting arithmetic flags.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RVM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv escrituraVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. RDX/EDX is implied 64/32 bits

Measured cost

Loading measurements from arch-data...

Description

Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand (the third operand) and stores the low half of the result in the second destination (second operand), the high half of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This enables efficient programming where the software can interleave add with carry operations and multiplications.

If the first and second operand are identical, it will contain the high half of the multiplication result.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

// DEST1: ModRM:reg
// DEST2: VEX.vvvv
IF (OperandSize = 32)

    SRC1 := EDX;
    DEST2 := (SRC1*SRC2)[31:0];
    DEST1 := (SRC1*SRC2)[63:32];
ELSE IF (OperandSize = 64)
    SRC1 := RDX;

          DEST2 := (SRC1*SRC2)[63:0];
          DEST1 := (SRC1*SRC2)[127:64];
FI

Intel C/C++ compiler intrinsics

Auto-generated from high-level language when possible. unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);
unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);

Flags affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, "Type 13 Class Exception Conditions."

Sources