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Source code

VFPCLASSSH

Test Types of Scalar FP16 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.LLIG.NP.0F3A.W0 67 /r /ibVFPCLASSSH k1{k2}, xmm1/m16, imm8AValidValidTest the input for the following categories: NaN, OR AVX10.1 +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8 lecturaimmediate byte after the instruction

Tupla: Scalar

Measured cost

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Description

This instruction checks the low FP16 value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against; see Table 5-12 for the categories. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in the destination mask register according to the writemask. The other bits in the destination mask register are zeroed.

Operation

// see VFPCLASSPH

VFPCLASSSH dest{k2}, src, imm8
IF k2[0] or *no writemask*:

    DEST.bit[0] := check_fp_class_fp16(src.fp16[0], imm8)
ELSE:

    DEST.bit[0] := 0

DEST[MAXKL-1:1] := 0

Intel C/C++ compiler intrinsics

VFPCLASSSH __mmask8 _mm_fpclass_sh_mask (__m128h a, int imm8);
VFPCLASSSH __mmask8 _mm_mask_fpclass_sh_mask (__mmask8 k1, __m128h a, int imm8);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instructions, see Table 2-60, "Type E10 Class Exception Conditions."

Sources