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Source code

VPBLENDMB, VPBLENDMW

Blend Byte/Word Vectors Using an Opmask Control

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.0F38.W0 66 /rVPBLENDMB xmm1 {k1}{z}, xmm2, xmm3/m128AValidValidBlend byte integer vector xmm2 and byte vector AVX512BW) OR xmm3/m128 and store the result in xmm1, under AVX10.1 control mask.
EVEX.256.66.0F38.W0 66 /rVPBLENDMB ymm1 {k1}{z}, ymm2, ymm3/m256AValidValidBlend byte integer vector ymm2 and byte vector AVX512BW) OR ymm3/m256 and store the result in ymm1, under AVX10.1 control mask.
EVEX.512.66.0F38.W0 66 /rVPBLENDMB zmm1 {k1}{z}, zmm2, zmm3/m512AValidValidBlend byte integer vector zmm2 and byte vector OR AVX10.1 zmm3/m512 and store the result in zmm1, under control mask.
EVEX.128.66.0F38.W1 66 /rVPBLENDMW xmm1 {k1}{z}, xmm2, xmm3/m128AValidValidBlend word integer vector xmm2 and word vector AVX512BW) OR xmm3/m128 and store the result in xmm1, under AVX10.1 control mask.
EVEX.256.66.0F38.W1 66 /rVPBLENDMW ymm1 {k1}{z}, ymm2, ymm3/m256AValidValidBlend word integer vector ymm2 and word vector AVX512BW) OR ymm3/m256 and store the result in ymm1, under AVX10.1 control mask.
EVEX.512.66.0F38.W1 66 /rVPBLENDMW zmm1 {k1}{z}, zmm2, zmm3/m512AValidValidBlend word integer vector zmm2 and word vector OR AVX10.1 zmm3/m512 and store the result in zmm1, under control mask.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full Mem

Measured cost

Loading measurements from arch-data...

Description

Performs an element-by-element blending of byte/word elements between the first source operand byte vector register and the second source operand byte vector from memory or register, using the instruction mask as selector. The result is written into the destination byte vector register.

The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.

The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every element of the destination is conditionally selected between first source or second source using the value of the related mask bit (0 for first source, 1 for second source).

Operation

VPBLENDMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

     THEN DEST[i+7:i] := SRC2[i+7:i]

     ELSE

             IF *merging-masking*                  ; merging-masking

                  THEN DEST[i+7:i] := SRC1[i+7:i]

                  ELSE                             ; zeroing-masking

                    DEST[i+7:i] := 0

             FI;

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0;

VPBLENDMW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

     THEN DEST[i+15:i] := SRC2[i+15:i]

     ELSE

             IF *merging-masking*                  ; merging-masking

                  THEN DEST[i+15:i] := SRC1[i+15:i]

                  ELSE                             ; zeroing-masking

                    DEST[i+15:i] := 0

             FI;

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);
VPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);
VPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);
VPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);
VPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);
VPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-51, "Type E4 Class Exception Conditions."

Sources