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Source code

VADDPH

Add Packed FP16 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.NP.MAP5.W0 58 /rVADDPH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidAdd packed FP16 value from AND AVX512VL) xmm3/m128/m16bcst to xmm2, and store result OR AVX10.1 in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 58 /rVADDPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidAdd packed FP16 value from AND AVX512VL) ymm3/m256/m16bcst to ymm2, and store result OR AVX10.1 in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 58 /rVADDPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidAdd packed FP16 value from OR AVX10.1 zmm3/m512/m16bcst to zmm2, and store result in zmm1 subject to writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

This instruction adds packed FP16 values from source operands and stores the packed FP16 result in the destination operand. The destination elements are updated according to the writemask.

Operation

VADDPH (EVEX Encoded Versions) When SRC2 Operand is a Register
VL = 128, 256 or 512
KL := VL/16
IF (VL = 512) AND (EVEX.b = 1):

    SET_RM(EVEX.RC)
ELSE

    SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:

    IF k1[j] OR *no writemask*:
          DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[j]

    ELSEIF *zeroing*:
          DEST.fp16[j] := 0

    // else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0


VADDPH (EVEX Encoded Versions) When SRC2 Operand is a Memory Source
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:

    IF k1[j] OR *no writemask*:
          IF EVEX.b = 1:
                DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[0]
          ELSE:
                DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[j]

    ELSE IF *zeroing*:
          DEST.fp16[j] := 0

    // else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VADDPH __m128h _mm_add_ph (__m128h a, __m128h b);
VADDPH __m128h _mm_mask_add_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VADDPH __m128h _mm_maskz_add_ph (__mmask8 k, __m128h a, __m128h b);
VADDPH __m256h _mm256_add_ph (__m256h a, __m256h b);
VADDPH __m256h _mm256_mask_add_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VADDPH __m256h _mm256_maskz_add_ph (__mmask16 k, __m256h a, __m256h b);
VADDPH __m512h _mm512_add_ph (__m512h a, __m512h b);
VADDPH __m512h _mm512_add_ph (__m512h a, __m512h b);
VADDPH __m512h _mm512_mask_add_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VADDPH __m512h _mm512_maskz_add_ph (__mmask32 k, __m512h a, __m512h b);
VADDPH __m512h _mm512_add_round_ph (__m512h a, __m512h b, int rounding);
VADDPH __m512h _mm512_mask_add_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);
VADDPH __m512h _mm512_maskz_add_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-48, "Type E2 Class Exception Conditions."

Sources