FIST, FISTP
Store Integer
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
DF /2 | FIST m16int | Valid | Valid | Store ST(0) in m16int. | |
DB /2 | FIST m32int | Valid | Valid | Store ST(0) in m32int. | |
DF /3 | FISTP m16int | Valid | Valid | Store ST(0) in m16int and pop register stack. | |
DB /3 | FISTP m32int | Valid | Valid | Store ST(0) in m32int and pop register stack. | |
DF /7 | FISTP m64int | Valid | Valid | Store ST(0) in m64int and pop register stack. |
Measured cost
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Description
The FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the destination operand. Values can be stored in word or doubleword integer format. The destination operand specifies the address where the first byte of the destination value is to be stored.
The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FISTP instruction also stores values in quadword integer format.
The following table shows the results obtained when storing various classes of numbers in integer format.
FIST/FISTP Results
| - | or Value Too Large for DEST Format | * |
|---|---|---|
| F -1 | -I | |
| -1 < F < -0 | ** | |
| -0 | 0 | |
| +0 | 0 | |
| +0<F<+1 | ** | |
| F+1 | +I | |
| + | or Value Too Large for DEST Format | * |
| NaN | * |
Operation
DEST := Integer(ST(0));
IF Instruction = FISTP
THEN
PopRegisterStack;
FI;
FPU Flags Affected
C1 Set to 0 if stack underflow occurred.
Indicates rounding direction of if the inexact exception (#P) is generated: 0 := not roundup; 1
:= roundup.
Set to 0 otherwise.
C0, C2, C3 Undefined.Floating-Point Exceptions
#IS Stack underflow occurred.#IA Converted value is too large for the destination format.Source operand is an SNaN, QNaN, +/-, or unsupported format.
#P Value cannot be represented exactly in destination format.Exceptions
Protected mode
#GP(0) | If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |
Real address mode
#GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
#UD | If the LOCK prefix is used. |
Virtual-8086 mode
#GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
#UD | If the LOCK prefix is used. |
Compatibility mode
| Same exceptions as in protected mode. |
64-bit mode
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
#GP(0) | If the memory address is in a non-canonical form. |
#NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
#MF | If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. |
#AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
#UD | If the LOCK prefix is used. |