CVTPI2PD
Convert Packed Dword Integers to Packed Double Precision Floating-Point Values
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
66 0F 2A /r | CVTPI2PD xmm, mm/m641 | RM | Valid | Valid | Convert two packed signed doubleword integers from mm/mem64 to two packed double precision floating-point values in xmm. |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RM
modrm.regescrituraModRM byte, reg field (bits 5-3)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
Measured cost
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Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed double precision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. In addition, depending on the operand configuration:
- For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PD instruction is executed.
- For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take
x87 FPU exceptions.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);Intel C/C++ compiler intrinsics
CVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a);SIMD Floating-Point Exceptions
None.
Other Exceptions
See Section 25.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers" in the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.