Vesta
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Source code

FTST

TEST

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
D9 E4FTSTValidValidCompare ST(0) with 0.0.

Measured cost

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Description

Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below).

FTST Results

ConditionC3C2C0
ST(0) > 0.0000
ST(0) < 0.0001
ST(0) = 0.0100
Unordered111

Operation

CASE (relation of operands) OF

    Not comparable: C3, C2, C0 := 111;

    ST(0) > 0.0:  C3, C2, C0 := 000;

    ST(0) < 0.0:  C3, C2, C0 := 001;

    ST(0) = 0.0:  C3, C2, C0 := 100;

ESAC;

FPU Flags Affected

C1                  Set to 0.

C0, C2, C3          See Table 3-42.

Floating-Point Exceptions

#IS                 Stack underflow occurred.
#IA                 The source operand is a NaN value or is in an unsupported format.
#D                  The source operand is a denormal value.

Exceptions

Protected mode
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
Real address mode
Same exceptions as in protected mode.
Virtual-8086 mode
Same exceptions as in protected mode.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
Same exceptions as in protected mode.

Sources