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Source code

GF2P8MULB

Galois Field Multiply Bytes

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F38 CF /rGF2P8MULB xmm1, xmm2/m128AValidValidMultiplies elements in the finite field GF(2^8).
VEX.128.66.0F38.W0 CF /rVGF2P8MULB xmm1, xmm2, xmm3/m128BValidValidMultiplies elements in the finite field GF(2^8). GFNI
VEX.256.66.0F38.W0 CF /rVGF2P8MULB ymm1, ymm2, ymm3/m256BValidValidMultiplies elements in the finite field GF(2^8). GFNI
EVEX.128.66.0F38.W0 CF /rVGF2P8MULB xmm1{k1}{z}, xmm2, xmm3/m128CValidValidMultiplies elements in the finite field GF(2^8). OR AVX10.1) GFNI
EVEX.256.66.0F38.W0 CF /rVGF2P8MULB ymm1{k1}{z}, ymm2, ymm3/m256CValidValidMultiplies elements in the finite field GF(2^8). OR AVX10.1) GFNI
EVEX.512.66.0F38.W0 CF /rVGF2P8MULB zmm1{k1}{z}, zmm2, zmm3/m512CValidValidMultiplies elements in the finite field GF(2^8). OR AVX10.1) GFNI

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

C

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full Mem

Measured cost

Loading measurements from arch-data...

Description

The instruction multiplies elements in the finite field GF(28), operating on a byte (field element) in the first source operand and the corresponding byte in a second source operand. The field GF(28) is represented in polynomial representation with the reduction polynomial x8 + x4 + x3 + x + 1.

This instruction does not support broadcasting.

The EVEX encoded form of this instruction supports memory fault suppression. The SSE encoded forms of the instruction require16B alignment on their memory operations.

Operation

define gf2p8mul_byte(src1byte, src2byte):

tword := 0
FOR i := 0 to 7:

IF src2byte.bit[i]:

           tword := tword XOR (src1byte<< i)

* carry out polynomial reduction by the characteristic polynomial p*

FOR i := 14 downto 8:
p := 0x11B << (i-8)
                                        *0x11B = 0000_0001_0001_1011 in binary*

IF tword.bit[i]:

           tword := tword XOR p

return tword.byte[0]

VGF2P8MULB dest, src1, src2 (EVEX Encoded Version)

(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1:

    IF k1[j] OR *no writemask*:
         DEST.byte[j] := gf2p8mul_byte(SRC1.byte[j], SRC2.byte[j])

    ELSE IF *zeroing*:
         DEST.byte[j] := 0

    * ELSE DEST.byte[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0

VGF2P8MULB dest, src1, src2 (128b and 256b VEX Encoded Versions)

(KL, VL) = (16, 128), (32, 256)
FOR j := 0 TO KL-1:

    DEST.byte[j] := gf2p8mul_byte(SRC1.byte[j], SRC2.byte[j])
DEST[MAX_VL-1:VL] := 0

GF2P8MULB srcdest, src1 (128b SSE Encoded Version)
FOR j := 0 TO 15:

    SRCDEST.byte[j] :=gf2p8mul_byte(SRCDEST.byte[j], SRC1.byte[j])

Intel C/C++ compiler intrinsics

(V)GF2P8MULB __m128i _mm_gf2p8mul_epi8(__m128i, __m128i);
(V)GF2P8MULB __m128i _mm_mask_gf2p8mul_epi8(__m128i, __mmask16, __m128i, __m128i);
(V)GF2P8MULB __m128i _mm_maskz_gf2p8mul_epi8(__mmask16, __m128i, __m128i);
VGF2P8MULB __m256i _mm256_gf2p8mul_epi8(__m256i, __m256i);
VGF2P8MULB __m256i _mm256_mask_gf2p8mul_epi8(__m256i, __mmask32, __m256i, __m256i);
VGF2P8MULB __m256i _mm256_maskz_gf2p8mul_epi8(__mmask32, __m256i, __m256i);
VGF2P8MULB __m512i _mm512_gf2p8mul_epi8(__m512i, __m512i);
VGF2P8MULB __m512i _mm512_mask_gf2p8mul_epi8(__m512i, __mmask64, __m512i, __m512i);
VGF2P8MULB __m512i _mm512_maskz_gf2p8mul_epi8(__mmask64, __m512i, __m512i);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Legacy-encoded and VEX-encoded: See Table 2-21, "Type 4 Class Exception Conditions." EVEX-encoded: See Table 2-51, "Type E4 Class Exception Conditions."

Sources