ANDN
Logical AND NOT
stableVMJITAOTinstruction
Encodings
| Opcode | Instruction | Op/En | 64-bit | Compat/Legacy | Description |
|---|---|---|---|---|---|
VEX.LZ.0F38.W0 F2 /r | ANDN r32a, r32b, r/m32 | RVM | Valid | Valid | Bitwise AND of inverted r32b with r/m32, store result in r32a. |
VEX.LZ. 0F38.W1 F2 /r | ANDN r64a, r64b, r/m64 | RVM | Valid | Not encodable | Bitwise AND of inverted r64b with r/m64, store result in r64a. |
Operand encoding
Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.
RVM
modrm.regescrituraModRM byte, reg field (bits 5-3)vex.vvvvlecturaVEX prefix, vvvv field (inverted)modrm.rmlecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
Measured cost
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Flags named
CFCarryPFParityAFAuxiliary carryZFZeroSFSignOFOverflow
Description
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the second source operand). The result is stored in the first operand (destination operand). This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
DEST := (NOT SRC1) bitwiseAND SRC2;
SF := DEST[OperandSize -1];
ZF := (DEST = 0);Flags affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-29, "Type 13 Class Exception Conditions."