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GF2P8AFFINEINVQB

Galois Field Affine Transformation Inverse

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F3A CF /r /ibGF2P8AFFINEINVQB xmm1, xmm2/m128, imm8AValidValidComputes inverse affine transformation in the finite field GF(2^8).
VEX.128.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB xmm1, xmm2, xmm3/m128, imm8BValidValidComputes inverse affine transformation in the GFNI finite field GF(2^8).
VEX.256.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB ymm1, ymm2, ymm3/m256, imm8BValidValidComputes inverse affine transformation in the GFNI finite field GF(2^8).
EVEX.128.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst, imm8CValidValidComputes inverse affine transformation in the OR AVX10.1) finite field GF(2^8). GFNI
EVEX.256.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8CValidValidComputes inverse affine transformation in the OR AVX10.1) finite field GF(2^8). GFNI
EVEX.512.66.0F3A.W1 CF /r /ibVGF2P8AFFINEINVQB zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8CValidValidComputes inverse affine transformation in the OR AVX10.1) finite field GF(2^8). GFNI

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg lectura y escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8 lecturaimmediate byte after the instruction

B

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8 lecturaimmediate byte after the instruction

C

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. evex.vvvv lecturaEVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  4. imm8 lecturaimmediate byte after the instruction

Tupla: Full

Measured cost

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Description

The AFFINEINVB instruction computes an affine transformation in the Galois Field 28. For this instruction, an affine transformation is defined by A * inv(x) + b where "A" is an 8 by 8 bit matrix, and "x" and "b" are 8-bit vectors. The inverse of the bytes in x is defined with respect to the reduction polynomial x8 + x4 + x3 + x + 1.

One SIMD register (operand 1) holds "x" as either 16, 32 or 64 8-bit vectors. A second SIMD (operand 2) register or memory operand contains 2, 4, or 8 "A" values, which are operated upon by the correspondingly aligned 8 "x" values in the first register. The "b" vector is constant for all calculations and contained in the immediate byte.

The EVEX encoded form of this instruction does not support memory fault suppression. The SSE encoded forms of the instruction require 16B alignment on their memory operations.

The inverse of each byte is given by the following table. The upper nibble is on the vertical axis and the lower nibble is on the horizontal axis. For example, the inverse of 0x95 is 0x8A.

Inverse Byte Listings

-0123456789ABCDEF
0018D F6CB527BD1E84F 29C0B0E1E5C7
174B4AA 4B992B605F583F FDCCFF40EEB2
23A6E5A F1554DA8C9C1A 98153044A2C2
32C4592 6CF3396642F235 206F77BB5919
41DFE37 672D31F569A764 AB135425E99
5ED5C5 CA4C2487BF183E 22F051EC6117
6165EAF D349A63643F447 91DF3393213B
779B797 8510B5BA3CB670 D06A1FA8182
8837E7F 809673BE569B9E 95D9F72B9A4
9DE 6A32 6DD88A84722A14 9F88F9DC899A
AFB7C2E C38FB8654826C8 124ACEE7D262
BCE01FEF11757871A58E 763DBDBC8657
CB282F A3DAD4E4FA927 5341BFCACE6
D7A7AE 63C5DBE2EA948B C4D59DF8906B
EB1DD6 EBC6ECFAD84E D7E35D501EB3
F5B2338 34684638CDD9C 7DA0CD1A411C

Operation

define affine_inverse_byte(tsrc2qw, src1byte, imm):
    FOR i := 0 to 7:
          * parity(x) = 1 if x has an odd number of 1s in it, and 0 otherwise.*
          * inverse(x) is defined in the table above *
         retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
    return retbyte

VGF2P8AFFINEINVQB dest, src1, src2, imm8 (EVEX Encoded Version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:

    IF SRC2 is memory and EVEX.b==1:
         tsrc2 := SRC2.qword[0]

    ELSE:
         tsrc2 := SRC2.qword[j]

FOR b := 0 to 7:
    IF k1[j*8+b] OR *no writemask*:
         FOR i := 0 to 7:
               DEST.qword[j].byte[b] := affine_inverse_byte(tsrc2, SRC1.qword[j].byte[b], imm8)
    ELSE IF *zeroing*:
         DEST.qword[j].byte[b] := 0
    *ELSE DEST.qword[j].byte[b] remains unchanged*

DEST[MAX_VL-1:VL] := 0


VGF2P8AFFINEINVQB dest, src1, src2, imm8 (128b and 256b VEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256)
FOR j := 0 TO KL-1:

    FOR b := 0 to 7:
         DEST.qword[j].byte[b] := affine_inverse_byte(SRC2.qword[j], SRC1.qword[j].byte[b], imm8)

DEST[MAX_VL-1:VL] := 0

GF2P8AFFINEINVQB srcdest, src1, imm8 (128b SSE Encoded Version)
FOR j := 0 TO 1:

    FOR b := 0 to 7:
         SRCDEST.qword[j].byte[b] := affine_inverse_byte(SRC1.qword[j], SRCDEST.qword[j].byte[b], imm8)

Intel C/C++ compiler intrinsics

(V)GF2P8AFFINEINVQB __m128i _mm_gf2p8affineinv_epi64_epi8(__m128i, __m128i, int);
(V)GF2P8AFFINEINVQB __m128i _mm_mask_gf2p8affineinv_epi64_epi8(__m128i, __mmask16, __m128i, __m128i, int);
(V)GF2P8AFFINEINVQB __m128i _mm_maskz_gf2p8affineinv_epi64_epi8(__mmask16, __m128i, __m128i, int);
VGF2P8AFFINEINVQB __m256i _mm256_gf2p8affineinv_epi64_epi8(__m256i, __m256i, int);
VGF2P8AFFINEINVQB __m256i _mm256_mask_gf2p8affineinv_epi64_epi8(__m256i, __mmask32, __m256i, __m256i, int);
VGF2P8AFFINEINVQB __m256i _mm256_maskz_gf2p8affineinv_epi64_epi8(__mmask32, __m256i, __m256i, int);
VGF2P8AFFINEINVQB __m512i _mm512_gf2p8affineinv_epi64_epi8(__m512i, __m512i, int);
VGF2P8AFFINEINVQB __m512i _mm512_mask_gf2p8affineinv_epi64_epi8(__m512i, __mmask64, __m512i, __m512i, int);
VGF2P8AFFINEINVQB __m512i _mm512_maskz_gf2p8affineinv_epi64_epi8(__mmask64, __m512i, __m512i, int);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Legacy-encoded and VEX-encoded: See Table 2-21, "Type 4 Class Exception Conditions."

EVEX-encoded: See Table 2-52, "Type E4NF Class Exception Conditions."

Sources