Vesta
English
Source code

MOVHLPS

Move Packed Single Precision Floating-Point Values High to Low

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
NP 0F 12 /rMOVHLPS xmm1, xmm2RMValidValidMove two packed single precision floating-point values from high quadword of xmm2 to low quadword of xmm1.
VEX.128.0F.WIG 12 /rVMOVHLPS xmm1, xmm2, xmm3RVMValidValidMerge two packed single precision floating-point values from high quadword of xmm3 and low quadword of xmm2.
EVEX.128.0F.W0 12 /rVMOVHLPS xmm1, xmm2, xmm3 Op/En Oper RM ModRM RVM ModRMRVMValidValidMerge two packed single precision floating-point values Instruction OR AVX10.1 Operand Encoding1 from high quadword of xmm3 and low quadword of xmm2. and 1 Operand 2 Operand 3 Operand 4 :reg (w) Mo dRM:r/m (r) N/A N/A :reg (w) VEX.vvvv (r) / EVEX.vvvv (r) ModRM:r/m (r) N/A

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

RVM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. VEX.vvvv (r) /
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

This instruction cannot be used for memory to register moves.

128-bit two-argument form:

Moves two packed single precision floating-point values from the high quadword of the second XMM argument (second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of the destination operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.

128-bit and EVEX three-argument form:

Moves two packed single precision floating-point values from the high quadword of the third XMM argument (third operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.

If VMOVHLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L'L= 1 will cause an #UD exception.

Operation

MOVHLPS (128-bit Two-Argument Form)
DEST[63:0] := SRC[127:64]
DEST[MAXVL-1:64] (Unmodified)

VMOVHLPS (128-bit Three-Argument Form - VEX & EVEX)
DEST[63:0] := SRC2[127:64]
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0

Intel C/C++ compiler intrinsics

MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b);

SIMD Floating-Point Exceptions

None.

  1. ModRM.MOD = 011B required.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-24, "Type 7 Class Exception Conditions," additionally:

#UD               If VEX.L = 1.

EVEX-encoded instruction, see Exceptions Type E7NM.128 in Table 2-57, "Type E7NM Class Exception Conditions."

Sources