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Source code

BNDMOV

Move Bounds

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F 1A /rBNDMOV bnd1, bnd2/m64RMNot encodableValidMove lower and upper bound from bnd2/m64 to bound register bnd1.
66 0F 1A /rBNDMOV bnd1, bnd2/m128RMValidNot encodableMove lower and upper bound from bnd2/m128 to bound register bnd1.
66 0F 1B /rBNDMOV bnd1/m64, bnd2MRNot encodableValidMove lower and upper bound from bnd2 to bnd1/m64.
66 0F 1B /rBNDMOV bnd1/m128, bnd2MRValidNot encodableMove lower and upper bound from bnd2 to bound register bnd1/m128.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

MR

  1. modrm.rm escrituraModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  2. modrm.reg lecturaModRM byte, reg field (bits 5-3)

Measured cost

Loading measurements from arch-data...

Description

BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.

                     Upper Bound (UB)             Lower Bound (LB)                     BNDMOV to memory in 64-bit mode
                     16                                             8                                           0 Byte offset
             Upper Bound (UB)                     Lower Bound (LB)                     BNDMOV to memory in 32-bit mode
             16                                                     8
                                                                                    4      0 Byte offset

Figure 3-5. Memory Layout of BNDMOV to/from Memory

This instruction does not change flags.

Operation

BNDMOV register to register
DEST.LB := SRC.LB;
DEST.UB := SRC.UB;


BNDMOV from memory
IF 64-bit mode THEN

          DEST.LB := LOAD_QWORD(SRC);
          DEST.UB := LOAD_QWORD(SRC+8);
    ELSE
          DEST.LB := LOAD_DWORD_ZERO_EXT(SRC);
          DEST.UB := LOAD_DWORD_ZERO_EXT(SRC+4);
FI;

BNDMOV to memory
IF 64-bit mode THEN

          DEST[63:0] := SRC.LB;
          DEST[127:64] := SRC.UB;
    ELSE
          DEST[31:0] := SRC.LB;
          DEST[63:32] := SRC.UB;
FI;

Intel C/C++ compiler intrinsics

BNDMOV void * _bnd_copy_ptr_bounds(const void *q, const void *r);

Flags affected

None.

Exceptions

Protected mode
#UDIf the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 67H prefix is not used and CS.D=0. If 67H prefix is used and CS.D=1.
#SS(0)If the memory operand effective address is outside the SS segment limit.
#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the destination operand points to a non-writable segment If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3. #PF(fault code) If a page fault occurs.
Real address mode
#UDIf the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 16-bit addressing is used.
#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SSIf the memory operand effective address is outside the SS segment limit.
Virtual-8086 mode
#UDIf the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled. If 16-bit addressing is used.
#GP(0)If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)If the memory operand effective address is outside the SS segment limit.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3. #PF(fault code) If a page fault occurs.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
#UDIf the LOCK prefix is used but the destination is not a memory operand. If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0)If the memory address referencing the SS segment is in a non-canonical form.
#GP(0)If the memory address is in a non-canonical form.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while CPL is 3. #PF(fault code) If a page fault occurs.

Sources