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Source code

PTWRITE

Write Data to a Processor Trace Packet

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
F3 REX.W 0F AE /4PTWRITE r64/m64RMValidn.eReads the data from r64/m64 to encode into a PTW packet if dependencies are met (see details below).
F3 0F AE /4PTWRITE r32/m32RMValidValidReads the data from r32/m32 to encode into a PTW packet if dependencies are met (see details below).

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

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Description

This instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded in a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3C, Section 36.2.2, "Software Trace Instrumentation with PTWRITE." The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data are copied from the source operand.

Note: The instruction will #UD if prefix 66H is used.

Operation

IF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1
    PTW.PayloadBytes := Encoded payload size;
    PTW.IP := IA32_RTIT_CTL.FUPonPTW
    IF IA32_RTIT_CTL.FUPonPTW = 1
          Insert FUP packet with IP of PTWRITE;
    FI;

FI;

Flags affected

None.

Exceptions

Protected mode
#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)If a memory operand effective address is outside the SS segment limit. #PF (fault-code) For a page fault.
#AC(0)If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled.
#UDIf CPUID.14H.00H:EBX.PTWRITE[4] = 0. If LOCK prefix is used. If 66H prefix is used.
Real address mode
#GP(0)If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)If a memory operand effective address is outside the SS segment limit.
#UDIf CPUID.14H.00H:EBX.PTWRITE[4] = 0. If LOCK prefix is used. If 66H prefix is used. Virtual 8086 Mode Exceptions
#GP(0)If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)If a memory operand effective address is outside the SS segment limit. #PF (fault-code) For a page fault.
#AC(0)If an unaligned memory reference is made while alignment checking is enabled.
#UDIf CPUID.14H.00H:EBX.PTWRITE[4] = 0. If LOCK prefix is used. If 66H prefix is used.
Compatibility mode
Same exceptions as in Protected Mode.
64-bit mode
#GP(0)If the memory address is in a non-canonical form.
#SS(0)If a memory address referencing the SS segment is in a non-canonical form. #PF (fault-code) For a page fault.
#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UDIf CPUID.14H.00H:EBX.PTWRITE[4] = 0. If LOCK prefix is used. If 66H prefix is used.

Sources