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Source code

PCMPISTRM

Packed Compare Implicit Length Strings, Return Mask

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
66 0F 3A 62 /r imm8PCMPISTRM xmm1, xmm2/m128, imm8RMValidValidPerform a packed comparison of string data with implicit lengths, generating a mask, and storing the result in XMM0.
VEX.128.66.0F3A.WIG 62 /r ibVPCMPISTRM xmm1, xmm2/m128, imm8RMValidValidPerform a packed comparison of string data with implicit lengths, generating a Mask, and storing the result in XMM0.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg lecturaModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them
  3. imm8immediate byte after the instruction

Measured cost

Loading measurements from arch-data...

Description

The instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1, "Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM") generating a mask stored to XMM0.

Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which contains the data elements of the string (byte or word data). Each input byte/word is augmented with a valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null byte/word. (The least significant null byte/word is also considered invalid.)

The comparison and aggregation operation are performed according to the encoded value of imm8 bit fields (see Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.

Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:

    CFlag  Reset if IntRes2 is equal to zero, set otherwise
    ZFlag  Set if any byte/word of xmm2/mem128 is null, reset otherwise
    SFlag  Set if any byte/word of xmm1 is null, reset otherwise
    OFlag  IntRes2[0]
    AFlag  Reset
    PFlag  Reset

Note: In VEX.128 encoded versions, bits (MAXVL-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.

Effective Operand Size

Operating mode/size Operand 1 Operand 2 Result 16 bit xmm xmm/m128 XMM0 32 bit xmm xmm/m128 XMM0 64 bit xmm xmm/m128 XMM0

Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask __m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);

Intel C/C++ Compiler Intrinsics For Reading EFlag Results

int _mm_cmpistra (__m128i a, __m128i b, const int mode); int _mm_cmpistrc (__m128i a, __m128i b, const int mode); int _mm_cmpistro (__m128i a, __m128i b, const int mode); int _mm_cmpistrs (__m128i a, __m128i b, const int mode); int _mm_cmpistrz (__m128i a, __m128i b, const int mode);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, "Type 4 Class Exception Conditions," additionally, this instruction does not cause #GP if the memory operand is not aligned to 16 Byte boundary, and:

#UD               If VEX.L = 1.
                  If VEX.vvvv  1111B.

Sources