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VSCALEFPH

Scale Packed FP16 Values with FP16 Values

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.66.MAP6.W0 2C /rVSCALEFPH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstAValidValidScale the packed FP16 values in xmm2 using AND AVX512VL) values from xmm3/m128/m16bcst, and store OR AVX10.1 the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP6.W0 2C /rVSCALEFPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstAValidValidScale the packed FP16 values in ymm2 using AND AVX512VL) values from ymm3/m256/m16bcst, and store the OR AVX10.1 result in ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0 2C /rVSCALEFPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}AValidValidScale the packed FP16 values in zmm2 using OR AVX10.1 values from zmm3/m512/m16bcst, and store the result in zmm1 subject to writemask k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

A

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. vex.vvvv lecturaVEX prefix, vvvv field (inverted)
  3. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Tupla: Full

Measured cost

Loading measurements from arch-data...

Description

This instruction performs a floating-point scale of the packed FP16 values in the first source operand by multiplying it by 2 to the power of the FP16 values in second source operand. The destination elements are updated according to the writemask.

The equation of this operation is given by:

     zmm1 := zmm2 * 2floor(zmm3).

Floor(zmm3) means maximum integer value zmm3.

If the result cannot be represented in FP16, then the proper overflow response (for positive scaling operand), or the proper underflow response (for negative scaling operand), is issued. The overflow and underflow responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception mask bits), and on the SAE bit.

Handling of special-case input values are listed in Table 5-39 and Table 5-40.

VSCALEFPH/VSCALEFSH Special Cases

+/-QNaNQNaN(Src1)+INF+0QNaN(Src1)IF either source is SNaN
+/-SNaNQNaN(Src1)QNaN(Src1)QNaN(Src1)QNaN(Src1)YES
+/-INFQNaN(Src2)Src1QNaN_IndefiniteSrc1IF Src2 is SNaN or -INF
+/-0QNaN(Src2)QNaN_IndefiniteSrc1Src1IF Src2 is SNaN or +INF

Operation

def scale_fp16(src1,src2):

    tmp1 := src1
    tmp2 := src2
    return tmp1 * POW(2, FLOOR(tmp2))

VSCALEFPH dest{k1}, src1, src2
VL = 128, 256, or 512
KL := VL / 16

IF (VL = 512) AND (EVEX.b = 1) and no memory operand:
    SET_RM(EVEX.RC)

ELSE
    SET_RM(MXCSR.RC)

FOR i := 0 to KL-1:
    IF k1[i] or *no writemask*:
          IF SRC2 is memory and (EVEX.b = 1):
                tsrc := src2.fp16[0]
          ELSE:
                tsrc := src2.fp16[i]
          dest.fp16[i] := scale_fp16(src1.fp16[i],tsrc)
    ELSE IF *zeroing*:
          dest.fp16[i] := 0
    //else dest.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VSCALEFPH __m128h _mm_mask_scalef_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VSCALEFPH __m128h _mm_maskz_scalef_ph (__mmask8 k, __m128h a, __m128h b);
VSCALEFPH __m128h _mm_scalef_ph (__m128h a, __m128h b);
VSCALEFPH __m256h _mm256_mask_scalef_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VSCALEFPH __m256h _mm256_maskz_scalef_ph (__mmask16 k, __m256h a, __m256h b);
VSCALEFPH __m256h _mm256_scalef_ph (__m256h a, __m256h b);
VSCALEFPH __m512h _mm512_mask_scalef_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VSCALEFPH __m512h _mm512_maskz_scalef_ph (__mmask32 k, __m512h a, __m512h b);
VSCALEFPH __m512h _mm512_scalef_ph (__m512h a, __m512h b);
VSCALEFPH __m512h _mm512_mask_scalef_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, const int rounding);
VSCALEFPH __m512h _mm512_scalef_round_ph (__m512h a, __m512h b, const int rounding);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal (for Src1).

Denormal is not reported for Src2.

Other Exceptions

EVEX-encoded instruction, see Table 2-48, "Type E2 Class Exception Conditions".

Sources