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VPMOVM2B, VPMOVM2W, VPMOVM2D, VPMOVM2Q

Convert a Mask Register to a Vector

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
EVEX.128.F3.0F38.W0 28 /rVPMOVM2B xmm1, k1RMValidValidSets each byte in XMM1 to all 1's or all 0's based on the AVX512BW) OR AVX10.1 value of the corresponding bit in k1.
EVEX.256.F3.0F38.W0 28 /rVPMOVM2B ymm1, k1RMValidValidSets each byte in YMM1 to all 1's or all 0's based on the AVX512BW) OR AVX10.1 value of the corresponding bit in k1.
EVEX.512.F3.0F38.W0 28 /rVPMOVM2B zmm1, k1RMValidValidSets each byte in ZMM1 to all 1's or all 0's based on the OR AVX10.1 value of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 28 /rVPMOVM2W xmm1, k1RMValidValidSets each word in XMM1 to all 1's or all 0's based on AVX512BW) OR AVX10.1 the value of the corresponding bit in k1.
EVEX.256.F3.0F38.W1 28 /rVPMOVM2W ymm1, k1RMValidValidSets each word in YMM1 to all 1's or all 0's based on AVX512BW) OR AVX10.1 the value of the corresponding bit in k1.
EVEX.512.F3.0F38.W1 28 /rVPMOVM2W zmm1, k1RMValidValidSets each word in ZMM1 to all 1's or all 0's based on OR AVX10.1 the value of the corresponding bit in k1.
EVEX.128.F3.0F38.W0 38 /rVPMOVM2D xmm1, k1RMValidValidSets each doubleword in XMM1 to all 1's or all 0's AVX512DQ) OR AVX10.1 based on the value of the corresponding bit in k1.
EVEX.256.F3.0F38.W0 38 /rVPMOVM2D ymm1, k1RMValidValidSets each doubleword in YMM1 to all 1's or all 0's based AVX512DQ) OR AVX10.1 on the value of the corresponding bit in k1.
EVEX.512.F3.0F38.W0 38 /rVPMOVM2D zmm1, k1RMValidValidSets each doubleword in ZMM1 to all 1's or all 0's based OR AVX10.1 on the value of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 38 /rVPMOVM2Q xmm1, k1RMValidValidSets each quadword in XMM1 to all 1's or all 0's based AVX512DQ) OR AVX10.1 on the value of the corresponding bit in k1.
EVEX.256.F3.0F38.W1 38 /rVPMOVM2Q ymm1, k1RMValidValidSets each quadword in YMM1 to all 1's or all 0's based AVX512DQ) OR AVX10.1 on the value of the corresponding bit in k1.
EVEX.512.F3.0F38.W1 38 /rVPMOVM2Q zmm1, k1RMValidValidSets each quadword in ZMM1 to all 1's or all 0's based OR AVX10.1 on the value of the corresponding bit in k1.

Operand encoding

Each mode is a value of the Op/En column above. It says which field of the encoded instruction carries each operand, in the order they are written, and whether the instruction reads it, writes it or both.

RM

  1. modrm.reg escrituraModRM byte, reg field (bits 5-3)
  2. modrm.rm lecturaModRM byte, r/m field (bits 2-0); with the SIB byte and the displacement when the mod field asks for them

Measured cost

Loading measurements from arch-data...

Description

Converts a mask register to a vector register. Each element in the destination register is set to all 1's or all 0's depending on the value of the corresponding bit in the source mask register. The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VPMOVM2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1

    i := j * 8
    IF SRC[j]

          THEN DEST[i+7:i] := -1
          ELSE DEST[i+7:i] := 0
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

VPMOVM2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1

    i := j * 16
    IF SRC[j]

          THEN DEST[i+15:i] := -1
          ELSE DEST[i+15:i] := 0
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

VPMOVM2D (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1

    i := j * 32
    IF SRC[j]

          THEN DEST[i+31:i] := -1
          ELSE DEST[i+31:i] := 0
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

VPMOVM2Q (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1

    i := j * 64
    IF SRC[j]

          THEN DEST[i+63:i] := -1
          ELSE DEST[i+63:i] := 0
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0

Intel C/C++ compiler intrinsics

VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );
VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );
VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );
VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );
VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );
VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );
VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );
VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );
VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );
VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );
VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-57, "Type E7NM Class Exception Conditions."

Additionally: If EVEX.vvvv != 1111B.

#UD

Sources