Vesta
English
Source code

FPREM

Partial Remainder

stableVMJITAOTinstruction

Encodings

OpcodeInstructionOp/En64-bitCompat/LegacyDescription
D9 F8FPREMValidValidReplace ST(0) with the remainder obtained from dividing ST(0) by ST(1).

Measured cost

Loading measurements from arch-data...

Description

Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following value:

Remainder := ST(0) - (Q  ST(1))

Here, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)] toward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is less than that of the modulus, unless a partial remainder was computed (as described below).

This instruction produces an exact result; the inexact-result exception does not occur and the rounding control has no effect. The following table shows the results obtained when computing the remainder of various classes of numbers, assuming that underflow does not occur.

FPREM Results

ST(0)-FST(0)-F or -0**-F or -0ST(0)NaN
-0-0-0**-0-0NaN
+0+0+0**+0+0NaN
+FST(0)+F or +0**+F or +0ST(0)NaN
+******NaN
NaNNaNNaNNaNNaNNaNNaNNaN

Operation

D := exponent(ST(0))  exponent(ST(1));

IF D < 64
    THEN
          Q := Integer(TruncateTowardZero(ST(0) / ST(1)));
          ST(0) := ST(0)  (ST(1)  Q);
          C2 := 0;
          C0, C3, C1 := LeastSignificantBits(Q); (* Q2, Q1, Q0 *)
    ELSE
          C2 := 1;
          N := An implementation-dependent number between 32 and 63;
          QQ := Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D - N)));
          ST(0) := ST(0)  (ST(1)  QQ  2(D - N));

FI;

FPU Flags Affected

C0                        Set to bit 2 (Q2) of the quotient.

C1                        Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0).

C2                        Set to 0 if reduction complete; set to 1 if incomplete.

C3                        Set to bit 1 (Q1) of the quotient.

Floating-Point Exceptions

#IS                       Stack underflow occurred.
#IA                       Source operand is an SNaN value, modulus is 0, dividend is , or unsupported format.
#D                        Source operand is a denormal value.
#U                        Result is too small for destination format.

Exceptions

Protected mode
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
Real address mode
Same exceptions as in protected mode.
Virtual-8086 mode
Same exceptions as in protected mode.
Compatibility mode
Same exceptions as in protected mode.
64-bit mode
Same exceptions as in protected mode.

Sources